diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 34dbe706ad1..3b7f7968a7a 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -69,6 +69,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::ANY_EXTEND:
   case ISD::BSWAP:
   case ISD::CTLZ:
+  case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
   case ISD::FABS:
diff --git a/test/CodeGen/Mips/ctlz-v.ll b/test/CodeGen/Mips/ctlz-v.ll
new file mode 100644
index 00000000000..270f404877e
--- /dev/null
+++ b/test/CodeGen/Mips/ctlz-v.ll
@@ -0,0 +1,19 @@
+; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
+
+define <2 x i32> @ctlzv2i32(<2 x i32> %x) {
+entry:
+; MIPS32: clz     $2, $4
+; MIPS32: jr      $ra
+; MIPS32: clz     $3, $5
+
+; MIPS64: clz     $2, $4
+; MIPS64: jr      $ra
+; MIPS64: clz     $3, $5
+
+  %ret = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
+  ret <2 x i32> %ret
+}
+