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Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is common. rdar://problem/9303592 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130338 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -317,6 +317,10 @@ protected:
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return 0;
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}
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virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
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return 0;
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}
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private:
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bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
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@ -164,8 +164,12 @@ unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
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Reg =
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getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
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} else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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// Try to emit the constant directly.
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Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
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if (CF->isZero()) {
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Reg = TargetMaterializeFloatZero(CF);
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} else {
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// Try to emit the constant directly.
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Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
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}
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if (!Reg) {
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// Try to emit the constant by using an integer constant with a cast.
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@ -124,6 +124,8 @@ private:
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unsigned TargetMaterializeAlloca(const AllocaInst *C);
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unsigned TargetMaterializeFloatZero(const ConstantFP *CF);
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/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
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/// computed in an SSE register, not on the X87 floating point stack.
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bool isScalarFPTypeInSSEReg(EVT VT) const {
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@ -2049,6 +2051,45 @@ unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
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return ResultReg;
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}
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unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
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MVT VT;
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if (!isTypeLegal(CF->getType(), VT))
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return false;
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// Get opcode and regclass for the given zero.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.SimpleTy) {
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default: return false;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::FsFLD0SS;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp032;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::FsFLD0SD;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp064;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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// No f80 support yet.
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return false;
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}
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
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return ResultReg;
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}
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/// TryToFoldLoad - The specified machine instr operand is a vreg, and that
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/// vreg is being provided by the specified load instruction. If possible,
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/// try to fold the load as an operand to the instruction, returning true if
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@ -225,3 +225,16 @@ if.else: ; preds = %entry
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; CHECK-NEXT: je
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}
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; Check that 0.0 is materialized using pxor
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define void @test18(float* %p1) {
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store float 0.0, float* %p1
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ret void
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; CHECK: test18:
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; CHECK: pxor
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}
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define void @test19(double* %p1) {
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store double 0.0, double* %p1
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ret void
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; CHECK: test19:
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; CHECK: pxor
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}
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