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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
Clean up some Release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -70,7 +70,6 @@ char HexagonExpandPredSpillCode::ID = 0;
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bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
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const HexagonInstrInfo *TII = QTM.getInstrInfo();
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const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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@ -84,7 +83,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
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if (Opc == Hexagon::STriw_pred) {
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// STriw_pred [R30], ofst, SrcReg;
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unsigned FP = MI->getOperand(0).getReg();
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assert(FP == RegInfo->getFrameRegister() &&
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assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(1).isImm() && "Not an offset");
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int Offset = MI->getOperand(1).getImm();
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@ -129,7 +128,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
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assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
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"Not a predicate register");
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unsigned FP = MI->getOperand(1).getReg();
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assert(FP == RegInfo->getFrameRegister() &&
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assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(2).isImm() && "Not an offset");
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int Offset = MI->getOperand(2).getImm();
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@ -461,7 +461,7 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
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} else if (VT == MVT::i64) {
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TRC = Hexagon::DoubleRegsRegisterClass;
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} else {
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assert(0 && "Cannot handle this register class");
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llvm_unreachable("Cannot handle this register class");
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}
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unsigned NewReg = RegInfo.createVirtualRegister(TRC);
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@ -553,10 +553,6 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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case Hexagon::JMPR:
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return false;
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return true;
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default:
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return true;
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}
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return true;
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@ -793,9 +789,8 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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case Hexagon::DEALLOC_RET_V4:
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return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
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Hexagon::DEALLOC_RET_cNotPt_V4;
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default:
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assert(false && "Unexpected predicable instruction");
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}
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llvm_unreachable("Unexpected predicable instruction");
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}
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@ -1243,8 +1238,8 @@ isValidOffset(const int Opcode, const int Offset) const {
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return true;
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}
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assert(0 && "No offset range is defined for this opcode. Please define it in \
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the above switch statement!");
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llvm_unreachable("No offset range is defined for this opcode. "
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"Please define it in the above switch statement!");
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}
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@ -58,18 +58,16 @@ const unsigned* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
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};
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switch(Subtarget.getHexagonArchVersion()) {
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case HexagonSubtarget::V1:
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break;
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case HexagonSubtarget::V2:
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return CalleeSavedRegsV2;
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break;
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case HexagonSubtarget::V3:
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case HexagonSubtarget::V4:
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return CalleeSavedRegsV3;
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break;
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default:
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const char *ErrorString =
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"Callee saved registers requested for unknown archtecture version";
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llvm_unreachable(ErrorString);
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}
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llvm_unreachable("Callee saved registers requested for unknown architecture "
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"version");
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}
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BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
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@ -106,18 +104,16 @@ HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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};
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switch(Subtarget.getHexagonArchVersion()) {
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case HexagonSubtarget::V1:
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break;
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case HexagonSubtarget::V2:
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return CalleeSavedRegClassesV2;
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break;
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case HexagonSubtarget::V3:
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case HexagonSubtarget::V4:
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return CalleeSavedRegClassesV3;
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break;
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default:
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const char *ErrorString =
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"Callee saved register classes requested for unknown archtecture version";
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llvm_unreachable(ErrorString);
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}
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llvm_unreachable("Callee saved register classes requested for unknown "
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"architecture version");
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}
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void HexagonRegisterInfo::
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@ -71,6 +71,8 @@ bool PTXMFInfoExtract::runOnMachineFunction(MachineFunction &MF) {
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RegType = PTXRegisterType::F32;
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else if (TRC == PTX::RegF64RegisterClass)
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RegType = PTXRegisterType::F64;
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else
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llvm_unreachable("Unkown register class.");
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MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg);
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}
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