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Clean up some Release build warnings.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-12-27 11:41:05 +00:00
parent 3738ccd7eb
commit 27baab62e7
4 changed files with 16 additions and 24 deletions
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5
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
View File

@ -70,7 +70,6 @@ char HexagonExpandPredSpillCode::ID = 0;
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonInstrInfo *TII = QTM.getInstrInfo();
const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
// Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@ -84,7 +83,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
assert(FP == RegInfo->getFrameRegister() &&
assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
@ -129,7 +128,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
assert(FP == RegInfo->getFrameRegister() &&
assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();

13
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -461,7 +461,7 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
} else if (VT == MVT::i64) {
TRC = Hexagon::DoubleRegsRegisterClass;
} else {
assert(0 && "Cannot handle this register class");
llvm_unreachable("Cannot handle this register class");
}
unsigned NewReg = RegInfo.createVirtualRegister(TRC);
@ -553,10 +553,6 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::JMPR:
return false;
return true;
default:
return true;
}
return true;
@ -793,9 +789,8 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
case Hexagon::DEALLOC_RET_V4:
return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
Hexagon::DEALLOC_RET_cNotPt_V4;
default:
assert(false && "Unexpected predicable instruction");
}
llvm_unreachable("Unexpected predicable instruction");
}
@ -1243,8 +1238,8 @@ isValidOffset(const int Opcode, const int Offset) const {
return true;
}
assert(0 && "No offset range is defined for this opcode. Please define it in \
the above switch statement!");
llvm_unreachable("No offset range is defined for this opcode. "
"Please define it in the above switch statement!");
}

20
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -58,18 +58,16 @@ const unsigned* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
};
switch(Subtarget.getHexagonArchVersion()) {
case HexagonSubtarget::V1:
break;
case HexagonSubtarget::V2:
return CalleeSavedRegsV2;
break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegsV3;
break;
default:
const char *ErrorString =
"Callee saved registers requested for unknown archtecture version";
llvm_unreachable(ErrorString);
}
llvm_unreachable("Callee saved registers requested for unknown architecture "
"version");
}
BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
@ -106,18 +104,16 @@ HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
};
switch(Subtarget.getHexagonArchVersion()) {
case HexagonSubtarget::V1:
break;
case HexagonSubtarget::V2:
return CalleeSavedRegClassesV2;
break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegClassesV3;
break;
default:
const char *ErrorString =
"Callee saved register classes requested for unknown archtecture version";
llvm_unreachable(ErrorString);
}
llvm_unreachable("Callee saved register classes requested for unknown "
"architecture version");
}
void HexagonRegisterInfo::

2
lib/Target/PTX/PTXMFInfoExtract.cpp
View File

@ -71,6 +71,8 @@ bool PTXMFInfoExtract::runOnMachineFunction(MachineFunction &MF) {
RegType = PTXRegisterType::F32;
else if (TRC == PTX::RegF64RegisterClass)
RegType = PTXRegisterType::F64;
else
llvm_unreachable("Unkown register class.");
MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg);
}