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Register sizes should be specified in bits

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16106 91177308-0d34-0410-b5e6-96231b3b80d8
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Nate Begeman 2004-08-29 22:03:40 +00:00
parent d332fd54f5
commit 27bc7c6cae
1 changed files with 2 additions and 2 deletions
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4
lib/Target/Skeleton/SkeletonRegisterInfo.td
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@ -77,10 +77,10 @@ def TBU : SPR<5>;
/// Register classes: one for floats and another for non-floats.
///
def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
def GPRC : RegisterClass<i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;