From 27bc818eaf73efe169f95c4dd8f564fd051dd824 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 24 Feb 2012 18:34:20 +0000 Subject: [PATCH] Add a -stress-regalloc= option. This will limit all register classes to N registers in order to stress test register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151379 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegisterClassInfo.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/RegisterClassInfo.cpp b/lib/CodeGen/RegisterClassInfo.cpp index 786d279c2b8..2fde16c4a2a 100644 --- a/lib/CodeGen/RegisterClassInfo.cpp +++ b/lib/CodeGen/RegisterClassInfo.cpp @@ -18,12 +18,16 @@ #include "RegisterClassInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetMachine.h" - +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; +cl::opt StressRA("stress-regalloc", cl::Hidden, cl::init(0), + cl::value_desc("N"), + cl::desc("Limit all regclasses to N registers")); + RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) {} @@ -99,6 +103,10 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { // CSR aliases go after the volatile registers, preserve the target's order. std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); + // Register allocator stress test. Clip register class to N registers. + if (StressRA && RCI.NumRegs > StressRA) + RCI.NumRegs = StressRA; + // Check if RC is a proper sub-class. if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)