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https://github.com/c64scene-ar/llvm-6502.git
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Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
e21710757d
commit
27eeb00a1a
@ -54,10 +54,7 @@ namespace {
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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// We don't support these yet.
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setOperationAction(ISD::FNEG , MVT::f64 , Expand);
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setOperationAction(ISD::FABS , MVT::f64 , Expand);
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setShiftAmountFlavor(Extend); // shl X, 32 == 0
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addLegalFPImmediate(+0.0); // Necessary for FSEL
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addLegalFPImmediate(-0.0); //
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@ -762,7 +759,22 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
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return Result;
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}
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case ISD::FNEG:
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if (ISD::FABS == N.getOperand(0).getOpcode()) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
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}
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return Result;
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case ISD::FABS:
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::FP_ROUND:
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assert (DestType == MVT::f32 &&
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N.getOperand(0).getValueType() == MVT::f64 &&
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@ -874,29 +886,34 @@ unsigned ISel::SelectExpr(SDOperand N) {
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unsigned &Reg = ExprMap[N];
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if (Reg) return Reg;
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if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
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N.getOpcode() != ISD::SUB_PARTS)
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switch (N.getOpcode()) {
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default:
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Reg = Result = (N.getValueType() != MVT::Other) ?
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MakeReg(N.getValueType()) : 1;
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else {
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MakeReg(N.getValueType()) : 1;
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break;
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case ISD::CALL:
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// If this is a call instruction, make sure to prepare ALL of the result
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// values as well as the chain.
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if (N.getOpcode() == ISD::CALL) {
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if (Node->getNumValues() == 1)
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Reg = Result = 1; // Void call, just a chain.
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else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
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}
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} else {
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if (Node->getNumValues() == 1)
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Reg = Result = 1; // Void call, just a chain.
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else {
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
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for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
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}
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break;
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case ISD::ADD_PARTS:
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case ISD::SUB_PARTS:
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case ISD::SHL_PARTS:
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case ISD::SRL_PARTS:
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case ISD::SRA_PARTS:
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Result = MakeReg(Node->getValueType(0));
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ExprMap[N.getValue(0)] = Result;
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for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
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ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
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break;
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}
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if (DestType == MVT::f64 || DestType == MVT::f32)
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@ -1265,11 +1282,71 @@ unsigned ISel::SelectExpr(SDOperand N) {
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for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
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InVals.push_back(SelectExpr(N.getOperand(i)));
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if (N.getOpcode() == ISD::ADD_PARTS) {
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BuildMI(BB, PPC::ADDC, 2, Result+1).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::ADDE, 2, Result).addReg(InVals[1]).addReg(InVals[3]);
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BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
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} else {
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BuildMI(BB, PPC::SUBFC, 2, Result+1).addReg(InVals[2]).addReg(InVals[0]);
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BuildMI(BB, PPC::SUBFE, 2, Result).addReg(InVals[3]).addReg(InVals[1]);
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BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
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BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
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}
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return Result+N.ResNo;
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}
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case ISD::SHL_PARTS:
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case ISD::SRA_PARTS:
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case ISD::SRL_PARTS: {
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assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
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"Not an i64 shift!");
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unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
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unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
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unsigned SHReg = SelectExpr(N.getOperand(2));
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Tmp1 = MakeReg(MVT::i32);
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Tmp2 = MakeReg(MVT::i32);
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Tmp3 = MakeReg(MVT::i32);
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unsigned Tmp4 = MakeReg(MVT::i32);
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unsigned Tmp5 = MakeReg(MVT::i32);
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unsigned Tmp6 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
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if (ISD::SHL_PARTS == opcode) {
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BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
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BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
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BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
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BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
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BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
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BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
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} else if (ISD::SRL_PARTS == opcode) {
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BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
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BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
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BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
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BuildMI(BB, PPC::SRW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
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BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp4).addReg(Tmp6);
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BuildMI(BB, PPC::SRW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
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} else {
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MachineBasicBlock *TmpMBB = new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *OldMBB = BB;
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MachineFunction *F = BB->getParent();
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ilist<MachineBasicBlock>::iterator It = BB; ++It;
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F->getBasicBlockList().insert(It, TmpMBB);
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F->getBasicBlockList().insert(It, PhiMBB);
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BB->addSuccessor(TmpMBB);
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BB->addSuccessor(PhiMBB);
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BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
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BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
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BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
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BuildMI(BB, PPC::ADDICo, 2, Tmp5).addReg(SHReg).addSImm(-32);
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BuildMI(BB, PPC::SRAW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
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BuildMI(BB, PPC::SRAW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
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BuildMI(BB, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
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// Select correct least significant half if the shift amount > 32
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BB = TmpMBB;
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unsigned Tmp7 = MakeReg(MVT::i32);
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BuildMI(BB, PPC::OR, 2, Tmp7).addReg(Tmp6).addReg(Tmp6);
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TmpMBB->addSuccessor(PhiMBB);
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BB = PhiMBB;
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BuildMI(BB, PPC::PHI, 4, Result).addReg(Tmp4).addMBB(OldMBB)
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.addReg(Tmp7).addMBB(TmpMBB);
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}
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return Result+N.ResNo;
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}
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@ -308,8 +308,12 @@ def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
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"fctidz $frD, $frB">;
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def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fctiwz $frD, $frB">;
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def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fabs $frD, $frB">;
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def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fmr $frD, $frB">;
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def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fnabs $frD, $frB">;
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def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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"fneg $frD, $frB">;
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def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
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