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[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6
Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210784 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
15aa07b2e8
commit
28002c2f82
@ -24,13 +24,13 @@ def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>;
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def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>,
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LW_FM_MM<0x2e>;
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def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
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LWXC1_FM_MM<0x48>;
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LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
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SWXC1_FM_MM<0x88>;
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SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
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def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
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LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2;
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LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
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def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
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SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2;
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SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
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def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
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CEQS_FM_MM<0>;
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@ -31,12 +31,6 @@ include "Mips32r6InstrFormats.td"
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// Removed: bgezal
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// Removed: bltzal
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// Removed: bc1[ft]
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// Removed: ldxc1
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// Removed: luxc1
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// Removed: lwxc1
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// Removed: sdxc1
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// Removed: suxc1
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// Removed: swxc1
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// Rencoded: [ls][wd]c2
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def brtarget21 : Operand<OtherVT> {
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@ -421,38 +421,38 @@ def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, ISA_MIPS2;
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// instruction mnemonic) is disallowed under NaCl.
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let AdditionalPredicates = [IsNotNaCl] in {
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def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
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INSN_MIPS4_32R2;
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INSN_MIPS4_32R2_NOT_32R6_64R6;
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def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
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INSN_MIPS4_32R2;
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INSN_MIPS4_32R2_NOT_32R6_64R6;
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}
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let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
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INSN_MIPS4_32R2, FGR_32;
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INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
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INSN_MIPS4_32R2, FGR_32;
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INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
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}
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let DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
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INSN_MIPS4_32R2, FGR_64;
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INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
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INSN_MIPS4_32R2, FGR_64;
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INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
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}
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// Load/store doubleword indexed unaligned.
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let AdditionalPredicates = [IsNotNaCl] in {
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def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
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INSN_MIPS5_32R2, FGR_32;
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INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
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def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
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INSN_MIPS5_32R2, FGR_32;
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INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
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}
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let DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
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INSN_MIPS5_32R2, FGR_64;
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INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
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INSN_MIPS5_32R2, FGR_64;
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INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
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}
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/// Floating-point Aritmetic
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@ -256,11 +256,17 @@ class INSN_MIPS4_32_NOT_32R6_64R6 {
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list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
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}
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// The portions of MIPS-IV that were also added to MIPS32R2
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class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
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// The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
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// MIPS32r6 and MIPS64r6.
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class INSN_MIPS4_32R2_NOT_32R6_64R6 {
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list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
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}
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// The portions of MIPS-V that were also added to MIPS32R2
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class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
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// The portions of MIPS-V that were also added to MIPS32r2 but were removed in
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// MIPS32r6 and MIPS64r6.
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class INSN_MIPS5_32R2_NOT_32R6_64R6 {
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list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
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}
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//===----------------------------------------------------------------------===//
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@ -1,6 +1,13 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
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; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s \
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; RUN: | FileCheck %s -check-prefix=CHECK-NACL
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2
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; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6
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; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6
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; Check that [ls][dwu]xc1 are not emitted for nacl.
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; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
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%struct.S = type <{ [4 x float] }>
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%struct.S2 = type <{ [4 x double] }>
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@ -14,8 +21,30 @@
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: lwxc1
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; ALL-LABEL: foo0:
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; MIPS32R1: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R1: lwc1 $f0, 0($[[T3]])
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; MIPS32R2: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R2: lwxc1 $f0, $[[T1]]($4)
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; MIPS32R6: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R6: lwc1 $f0, 0($[[T3]])
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; MIPS4: sll $[[T0:[0-9]+]], $5, 0
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; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 2
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; MIPS4: lwxc1 $f0, $[[T1]]($4)
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; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
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; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 2
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; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS64R6: lwc1 $f0, 0($[[T3]])
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; CHECK-NACL-NOT: lwxc1
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%arrayidx = getelementptr inbounds float* %b, i32 %o
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%0 = load float* %arrayidx, align 4
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ret float %0
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@ -23,8 +52,30 @@ entry:
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define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; CHECK: ldxc1
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; ALL-LABEL: foo1:
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; MIPS32R1: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R1: ldc1 $f0, 0($[[T3]])
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; MIPS32R2: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R2: ldxc1 $f0, $[[T1]]($4)
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; MIPS32R6: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R6: ldc1 $f0, 0($[[T3]])
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; MIPS4: sll $[[T0:[0-9]+]], $5, 0
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; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 3
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; MIPS4: ldxc1 $f0, $[[T1]]($4)
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; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
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; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 3
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; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS64R6: ldc1 $f0, 0($[[T3]])
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; CHECK-NACL-NOT: ldxc1
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%arrayidx = getelementptr inbounds double* %b, i32 %o
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%0 = load double* %arrayidx, align 8
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ret double %0
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@ -32,7 +83,23 @@ entry:
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK-NOT: luxc1
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; ALL-LABEL: foo2:
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; luxc1 did not exist in MIPS32r1
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; MIPS32R1-NOT: luxc1
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; luxc1 is a misnomer since it aligns the given pointer downwards and performs
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; an aligned load. We mustn't use it to handle unaligned loads.
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; MIPS32R2-NOT: luxc1
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; luxc1 was removed in MIPS32r6
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; MIPS32R6-NOT: luxc1
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; MIPS4-NOT: luxc1
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; luxc1 was removed in MIPS64r6
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; MIPS64R6-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%0 = load float* %arrayidx1, align 1
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ret float %0
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@ -40,8 +107,28 @@ entry:
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define void @foo3(float* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: swxc1
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; ALL-LABEL: foo3:
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; MIPS32R1-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]])
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; MIPS32R2: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R2: swxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS32R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]])
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; MIPS4: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS4: swxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS64R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
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; CHECK-NACL-NOT: swxc1
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%0 = load float* @gf, align 4
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%arrayidx = getelementptr inbounds float* %b, i32 %o
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store float %0, float* %arrayidx, align 4
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@ -50,8 +137,28 @@ entry:
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define void @foo4(double* nocapture %b, i32 %o) nounwind {
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entry:
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; CHECK: sdxc1
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; ALL-LABEL: foo4:
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; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R1-DAG: sdc1 $[[T0]], 0($[[T1]])
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; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R2: sdxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R6-DAG: sdc1 $[[T0]], 0($[[T1]])
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; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS4: sdxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS64R6-DAG: sdc1 $[[T0]], 0($[[T1]])
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; CHECK-NACL-NOT: sdxc1
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%0 = load double* @gd, align 8
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%arrayidx = getelementptr inbounds double* %b, i32 %o
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store double %0, double* %arrayidx, align 8
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@ -60,7 +167,18 @@ entry:
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK-NOT: suxc1
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; ALL-LABEL: foo5:
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; MIPS32R1-NOT: suxc1
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; MIPS32R2-NOT: suxc1
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; MIPS32R6-NOT: suxc1
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; MIPS4-NOT: suxc1
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; MIPS64R6-NOT: suxc1
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%0 = load float* @gf, align 4
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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store float %0, float* %arrayidx1, align 1
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@ -69,8 +187,18 @@ entry:
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK: foo6
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; CHECK-NOT: luxc1
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; ALL-LABEL: foo6:
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; MIPS32R1-NOT: luxc1
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; MIPS32R2-NOT: luxc1
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; MIPS32R6-NOT: luxc1
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; MIPS4-NOT: luxc1
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; MIPS64R6-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%0 = load double* %arrayidx1, align 1
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ret double %0
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@ -78,8 +206,18 @@ entry:
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK: foo7
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; CHECK-NOT: suxc1
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; ALL-LABEL: foo7:
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; MIPS32R1-NOT: suxc1
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; MIPS32R2-NOT: suxc1
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; MIPS32R6-NOT: suxc1
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; MIPS4-NOT: suxc1
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; MIPS64R6-NOT: suxc1
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%0 = load double* @gd, align 8
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
|
||||
store double %0, double* %arrayidx1, align 1
|
||||
@ -88,16 +226,36 @@ entry:
|
||||
|
||||
define float @foo8() nounwind readonly {
|
||||
entry:
|
||||
; CHECK: foo8
|
||||
; CHECK-NOT: luxc1
|
||||
; ALL-LABEL: foo8:
|
||||
|
||||
; MIPS32R1-NOT: luxc1
|
||||
|
||||
; MIPS32R2-NOT: luxc1
|
||||
|
||||
; MIPS32R6-NOT: luxc1
|
||||
|
||||
; MIPS4-NOT: luxc1
|
||||
|
||||
; MIPS64R6-NOT: luxc1
|
||||
|
||||
%0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define void @foo9(float %f) nounwind {
|
||||
entry:
|
||||
; CHECK: foo9
|
||||
; CHECK-NOT: suxc1
|
||||
; ALL-LABEL: foo9:
|
||||
|
||||
; MIPS32R1-NOT: suxc1
|
||||
|
||||
; MIPS32R2-NOT: suxc1
|
||||
|
||||
; MIPS32R6-NOT: suxc1
|
||||
|
||||
; MIPS4-NOT: suxc1
|
||||
|
||||
; MIPS64R6-NOT: suxc1
|
||||
|
||||
store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,110 +0,0 @@
|
||||
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
|
||||
|
||||
%struct.S = type <{ [4 x float] }>
|
||||
%struct.S2 = type <{ [4 x double] }>
|
||||
%struct.S3 = type <{ i8, float }>
|
||||
|
||||
@s = external global [4 x %struct.S]
|
||||
@gf = external global float
|
||||
@gd = external global double
|
||||
@s2 = external global [4 x %struct.S2]
|
||||
@s3 = external global %struct.S3
|
||||
|
||||
define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
|
||||
entry:
|
||||
; CHECK: lwxc1
|
||||
%idxprom = zext i32 %o to i64
|
||||
%arrayidx = getelementptr inbounds float* %b, i64 %idxprom
|
||||
%0 = load float* %arrayidx, align 4
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
|
||||
entry:
|
||||
; CHECK: ldxc1
|
||||
%idxprom = zext i32 %o to i64
|
||||
%arrayidx = getelementptr inbounds double* %b, i64 %idxprom
|
||||
%0 = load double* %arrayidx, align 8
|
||||
ret double %0
|
||||
}
|
||||
|
||||
define float @foo2(i32 %b, i32 %c) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-NOT: luxc1
|
||||
%idxprom = zext i32 %c to i64
|
||||
%idxprom1 = zext i32 %b to i64
|
||||
%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
|
||||
%0 = load float* %arrayidx2, align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define void @foo3(float* nocapture %b, i32 %o) nounwind {
|
||||
entry:
|
||||
; CHECK: swxc1
|
||||
%0 = load float* @gf, align 4
|
||||
%idxprom = zext i32 %o to i64
|
||||
%arrayidx = getelementptr inbounds float* %b, i64 %idxprom
|
||||
store float %0, float* %arrayidx, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo4(double* nocapture %b, i32 %o) nounwind {
|
||||
entry:
|
||||
; CHECK: sdxc1
|
||||
%0 = load double* @gd, align 8
|
||||
%idxprom = zext i32 %o to i64
|
||||
%arrayidx = getelementptr inbounds double* %b, i64 %idxprom
|
||||
store double %0, double* %arrayidx, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo5(i32 %b, i32 %c) nounwind {
|
||||
entry:
|
||||
; CHECK-NOT: suxc1
|
||||
%0 = load float* @gf, align 4
|
||||
%idxprom = zext i32 %c to i64
|
||||
%idxprom1 = zext i32 %b to i64
|
||||
%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
|
||||
store float %0, float* %arrayidx2, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define double @foo6(i32 %b, i32 %c) nounwind readonly {
|
||||
entry:
|
||||
; CHECK: foo6
|
||||
; CHECK-NOT: luxc1
|
||||
%idxprom = zext i32 %c to i64
|
||||
%idxprom1 = zext i32 %b to i64
|
||||
%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
|
||||
%0 = load double* %arrayidx2, align 1
|
||||
ret double %0
|
||||
}
|
||||
|
||||
define void @foo7(i32 %b, i32 %c) nounwind {
|
||||
entry:
|
||||
; CHECK: foo7
|
||||
; CHECK-NOT: suxc1
|
||||
%0 = load double* @gd, align 8
|
||||
%idxprom = zext i32 %c to i64
|
||||
%idxprom1 = zext i32 %b to i64
|
||||
%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
|
||||
store double %0, double* %arrayidx2, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define float @foo8() nounwind readonly {
|
||||
entry:
|
||||
; CHECK: foo8
|
||||
; CHECK-NOT: luxc1
|
||||
%0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
|
||||
ret float %0
|
||||
}
|
||||
|
||||
define void @foo9(float %f) nounwind {
|
||||
entry:
|
||||
; CHECK: foo9
|
||||
; CHECK-NOT: suxc1
|
||||
store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,33 +1,113 @@
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r2 \
|
||||
; RUN: < %s | FileCheck %s -check-prefix=LE-PIC
|
||||
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=LE-STATIC
|
||||
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=BE-PIC
|
||||
; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too.
|
||||
; RUN: llc -march=mipsel -mcpu=mips32 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=CHECK-LDC1-SDC1
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2-LDXC1
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1
|
||||
|
||||
; Check that -mno-ldc1-sdc1 disables [sl]dc1
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
|
||||
; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r2 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
|
||||
; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC
|
||||
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r6 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
|
||||
; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC
|
||||
|
||||
; Check again for big-endian
|
||||
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
|
||||
; RUN: -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC
|
||||
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r2 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
|
||||
; RUN: -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC
|
||||
; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r6 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
|
||||
; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC
|
||||
|
||||
; Check again for the static relocation model
|
||||
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \
|
||||
; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-STATIC
|
||||
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r2 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \
|
||||
; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-STATIC
|
||||
; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
|
||||
; RUN: -mcpu=mips32r6 < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
|
||||
; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC
|
||||
|
||||
@g0 = common global double 0.000000e+00, align 8
|
||||
|
||||
; LE-PIC-LABEL: test_ldc1:
|
||||
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; LE-PIC-DAG: mtc1 $[[R0]], $f0
|
||||
; LE-PIC-DAG: mthc1 $[[R1]], $f0
|
||||
; LE-STATIC-LABEL: test_ldc1:
|
||||
; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
|
||||
; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
|
||||
; LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
|
||||
; LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
|
||||
; LE-STATIC-DAG: mtc1 $[[R1]], $f0
|
||||
; LE-STATIC-DAG: mtc1 $[[R3]], $f1
|
||||
; BE-PIC-LABEL: test_ldc1:
|
||||
; BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; BE-PIC-DAG: mtc1 $[[R1]], $f0
|
||||
; BE-PIC-DAG: mtc1 $[[R0]], $f1
|
||||
; CHECK-LDC1-SDC1-LABEL: test_ldc1:
|
||||
; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
|
||||
; ALL-LABEL: test_ldc1:
|
||||
|
||||
; 32R1-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R1-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1
|
||||
|
||||
; 32R2-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R2-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0
|
||||
|
||||
; 32R6-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R6-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0
|
||||
|
||||
; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
|
||||
; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
|
||||
; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
|
||||
; 32R1-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
|
||||
; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
|
||||
|
||||
; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
|
||||
; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
|
||||
; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
|
||||
; 32R2-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
|
||||
; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0
|
||||
|
||||
; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
|
||||
; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
|
||||
; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
|
||||
; 32R6-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]])
|
||||
; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0
|
||||
|
||||
; 32R1-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R1-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1
|
||||
|
||||
; 32R2-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R2-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R2-BE-PIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0
|
||||
|
||||
; 32R6-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R6-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R6-BE-PIC-DAG: mtc1 $[[R1]], $f0
|
||||
; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0
|
||||
|
||||
; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
|
||||
|
||||
; 32R2-LDXC1: ldc1 $f0, 0(${{[0-9]+}})
|
||||
|
||||
; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
|
||||
|
||||
define double @test_ldc1() {
|
||||
entry:
|
||||
@ -35,25 +115,64 @@ entry:
|
||||
ret double %0
|
||||
}
|
||||
|
||||
; LE-PIC-LABEL: test_sdc1:
|
||||
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
; LE-STATIC-LABEL: test_sdc1:
|
||||
; LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
|
||||
; LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
|
||||
; LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
|
||||
; LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
|
||||
; BE-PIC-LABEL: test_sdc1:
|
||||
; BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
|
||||
; BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
|
||||
; CHECK-LDC1-SDC1-LABEL: test_sdc1:
|
||||
; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
|
||||
; ALL-LABEL: test_sdc1:
|
||||
|
||||
; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R1-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R1-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R2-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
|
||||
; 32R6-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R6-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R1-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R1-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
|
||||
; 32R1-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
|
||||
; 32R1-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
|
||||
; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
|
||||
|
||||
; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R2-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
|
||||
; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
|
||||
; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
|
||||
; 32R2-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
|
||||
|
||||
; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
|
||||
; 32R6-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0)
|
||||
; 32R6-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]])
|
||||
; 32R6-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0)
|
||||
; 32R6-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
|
||||
|
||||
; 32R1-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R1-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R1-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
|
||||
; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R2-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
|
||||
; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R6-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R6-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12
|
||||
; 32R6-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}})
|
||||
; 32R6-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
||||
|
||||
; 32R2-LDXC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
||||
|
||||
; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
||||
|
||||
define void @test_sdc1(double %a) {
|
||||
entry:
|
||||
@ -61,14 +180,35 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; ALL-LABEL: test_ldxc1:
|
||||
|
||||
; LE-PIC-LABEL: test_ldxc1:
|
||||
; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; LE-PIC-DAG: mtc1 $[[R0]], $f0
|
||||
; LE-PIC-DAG: mthc1 $[[R1]], $f0
|
||||
; CHECK-LDC1-SDC1-LABEL: test_ldxc1:
|
||||
; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}}
|
||||
; 32R1-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R1-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R1-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R1-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R1-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R1-DAG: mtc1 $[[R1]], $f1
|
||||
|
||||
; 32R2-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R2-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R2-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R2-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R2-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R2-DAG: mthc1 $[[R1]], $f0
|
||||
|
||||
; 32R6-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R6-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R6-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}})
|
||||
; 32R6-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}})
|
||||
; 32R6-DAG: mtc1 $[[R0]], $f0
|
||||
; 32R6-DAG: mthc1 $[[R1]], $f0
|
||||
|
||||
; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
|
||||
|
||||
; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $5, 3
|
||||
; 32R2-LDXC1: ldxc1 $f0, $[[OFFSET]]($4)
|
||||
|
||||
; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
|
||||
|
||||
define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
|
||||
entry:
|
||||
@ -77,13 +217,29 @@ entry:
|
||||
ret double %0
|
||||
}
|
||||
|
||||
; LE-PIC-LABEL: test_sdxc1:
|
||||
; LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
; CHECK-LDC1-SDC1-LABEL: test_sdxc1:
|
||||
; CHECK-LDC1-SDC1: sdxc1 $f{{[0-9]+}}
|
||||
; ALL-LABEL: test_sdxc1:
|
||||
|
||||
; 32R1-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R1-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R1-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R2-DAG: mfc1 $[[R1:[0-9]+]], $f13
|
||||
; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R6-DAG: mfc1 $[[R0:[0-9]+]], $f12
|
||||
; 32R6-DAG: mfhc1 $[[R1:[0-9]+]], $f12
|
||||
; 32R6-DAG: sw $[[R0]], 0(${{[0-9]+}})
|
||||
; 32R6-DAG: sw $[[R1]], 4(${{[0-9]+}})
|
||||
|
||||
; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
||||
|
||||
; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $7, 3
|
||||
; 32R2-LDXC1: sdxc1 $f{{[0-9]+}}, $[[OFFSET]]($6)
|
||||
|
||||
; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
||||
|
||||
define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
|
||||
entry:
|
||||
|
||||
11
test/MC/Mips/mips32r6/invalid-mips4.s
Normal file
11
test/MC/Mips/mips32r6/invalid-mips4.s
Normal file
@ -0,0 +1,11 @@
|
||||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
9
test/MC/Mips/mips32r6/invalid-mips5.s
Normal file
9
test/MC/Mips/mips32r6/invalid-mips5.s
Normal file
@ -0,0 +1,9 @@
|
||||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
11
test/MC/Mips/mips64r6/invalid-mips4.s
Normal file
11
test/MC/Mips/mips64r6/invalid-mips4.s
Normal file
@ -0,0 +1,11 @@
|
||||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
9
test/MC/Mips/mips64r6/invalid-mips5.s
Normal file
9
test/MC/Mips/mips64r6/invalid-mips5.s
Normal file
@ -0,0 +1,9 @@
|
||||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
Loading…
Reference in New Issue
Block a user