From 280f96c508c3f1a37732ce3b22323083ff029fc1 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Thu, 5 Aug 2010 18:36:20 +0000 Subject: [PATCH] Be a little bit more specific about target for the memory barrier instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110360 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86Instr64bit.td | 3 ++- lib/Target/X86/X86InstrInfo.td | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 04b75f9f8bc..4e2710b2ee5 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1624,7 +1624,8 @@ let Defs = [ESP] in def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero), "lock\n\t" "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", - [(X86MemBarrierNoSSE GR64:$zero)]>, LOCK; + [(X86MemBarrierNoSSE GR64:$zero)]>, + Requires<[In64BitMode]>, LOCK; let Defs = [RAX, EFLAGS], Uses = [RAX] in { def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 5fc1bb7be1b..b0e6b651ce1 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -3938,7 +3938,8 @@ let Defs = [ESP] in def Int_MemBarrierNoSSE : I<0x09, MRM1r, (outs), (ins GR32:$zero), "lock\n\t" "or{l}\t{$zero, (%esp)|(%esp), $zero}", - [(X86MemBarrierNoSSE GR32:$zero)]>, LOCK; + [(X86MemBarrierNoSSE GR32:$zero)]>, + Requires<[In32BitMode]>, LOCK; } // Atomic swap. These are just normal xchg instructions. But since a memory