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R600/SI: Fix printing of clamp and omod
No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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532a5c7dc6
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@ -294,6 +294,23 @@ void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
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printIfSet(MI, OpNo, O, "_SAT");
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printIfSet(MI, OpNo, O, "_SAT");
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}
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}
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void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " clamp";
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}
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void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int Imm = MI->getOperand(OpNo).getImm();
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if (Imm == SIOutMods::MUL2)
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O << " mul:2";
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else if (Imm == SIOutMods::MUL4)
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O << " mul:4";
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else if (Imm == SIOutMods::DIV2)
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O << " div:2";
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}
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void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
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void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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raw_ostream &O) {
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int32_t Imm = MI->getOperand(OpNo).getImm();
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int32_t Imm = MI->getOperand(OpNo).getImm();
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@ -52,6 +52,8 @@ private:
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StringRef Asm, StringRef Default = "");
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StringRef Asm, StringRef Default = "");
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static void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printClampSI(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printOModSI(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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@ -43,6 +43,15 @@ namespace SISrcMods {
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};
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};
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}
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}
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namespace SIOutMods {
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enum {
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NONE = 0,
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MUL2 = 1,
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MUL4 = 2,
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DIV2 = 3
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};
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}
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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@ -185,6 +185,14 @@ def tfe : Operand <i1> {
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let PrintMethod = "printTFE";
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let PrintMethod = "printTFE";
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}
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}
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def omod : Operand <i32> {
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let PrintMethod = "printOModSI";
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}
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def ClampMod : Operand <i1> {
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let PrintMethod = "printClampSI";
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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} // End OperandType = "OPERAND_IMMEDIATE"
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -399,7 +407,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
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!if (!eq(HasModifiers, 1),
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!if (!eq(HasModifiers, 1),
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// VOP1 with modifiers
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// VOP1 with modifiers
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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i32imm:$clamp, i32imm:$omod)
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ClampMod:$clamp, omod:$omod)
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/* else */,
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/* else */,
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// VOP1 without modifiers
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// VOP1 without modifiers
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(ins Src0RC:$src0)
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(ins Src0RC:$src0)
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@ -409,7 +417,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
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// VOP 2 with modifiers
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// VOP 2 with modifiers
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
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InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
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i32imm:$clamp, i32imm:$omod)
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ClampMod:$clamp, omod:$omod)
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/* else */,
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/* else */,
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// VOP2 without modifiers
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// VOP2 without modifiers
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(ins Src0RC:$src0, Src1RC:$src1)
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(ins Src0RC:$src0, Src1RC:$src1)
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@ -420,7 +428,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
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InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
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InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
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InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
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i32imm:$clamp, i32imm:$omod)
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ClampMod:$clamp, omod:$omod)
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/* else */,
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/* else */,
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// VOP3 without modifiers
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// VOP3 without modifiers
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(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
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(ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
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@ -442,12 +450,14 @@ class getAsm32 <int NumSrcArgs> {
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// instruction.
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// instruction.
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class getAsm64 <int NumSrcArgs, bit HasModifiers> {
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class getAsm64 <int NumSrcArgs, bit HasModifiers> {
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string src0 = "$src0_modifiers,";
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string src0 = "$src0_modifiers,";
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string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,");
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string src1 = !if(!eq(NumSrcArgs, 1), "",
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string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", "");
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!if(!eq(NumSrcArgs, 2), " $src1_modifiers",
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" $src1_modifiers,"));
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string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
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string ret =
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string ret =
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!if(!eq(HasModifiers, 0),
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!if(!eq(HasModifiers, 0),
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getAsm32<NumSrcArgs>.ret,
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getAsm32<NumSrcArgs>.ret,
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" $dst, "#src0#src1#src2#" $clamp, $omod");
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" $dst, "#src0#src1#src2#"$clamp"#"$omod");
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}
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}
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@ -632,7 +642,7 @@ multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
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P.Ins64, P.Asm64,
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P.Ins64, P.Asm64,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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[(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
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i32:$src0_modifiers, i32:$clamp, i32:$omod))))],
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i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
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P.HasModifiers
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P.HasModifiers
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>;
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>;
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@ -664,7 +674,7 @@ multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod)),
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOp, P.HasModifiers
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revOp, P.HasModifiers
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@ -692,7 +702,7 @@ multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod)),
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOp, P.HasModifiers
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revOp, P.HasModifiers
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@ -719,7 +729,7 @@ multiclass VOPCInst <bits<8> op, string opName,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set i1:$dst,
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[(set i1:$dst,
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(setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod)),
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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cond))],
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cond))],
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[(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
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[(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
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@ -767,7 +777,7 @@ multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod)),
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
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@ -776,14 +786,14 @@ multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod)),
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
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/* P.NumSrcArgs == 1 */,
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/* P.NumSrcArgs == 1 */,
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!if(P.HasModifiers,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i32:$clamp, i32:$omod))))],
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i1:$clamp, i32:$omod))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
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P.NumSrcArgs, P.HasModifiers
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P.NumSrcArgs, P.HasModifiers
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>;
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>;
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@ -795,8 +805,8 @@ multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
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(ins InputModsNoDefault:$src0_modifiers, arc:$src0,
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(ins InputModsNoDefault:$src0_modifiers, arc:$src0,
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InputModsNoDefault:$src1_modifiers, arc:$src1,
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InputModsNoDefault:$src1_modifiers, arc:$src1,
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InputModsNoDefault:$src2_modifiers, arc:$src2,
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InputModsNoDefault:$src2_modifiers, arc:$src2,
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i32imm:$clamp, i32imm:$omod),
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ClampMod:$clamp, i32imm:$omod),
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opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers, $clamp, $omod", pattern,
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opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
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opName, opName, 1, 1
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opName, opName, 1, 1
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>;
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>;
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@ -808,13 +818,13 @@ multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
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class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
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class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)),
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
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(Inst i32:$src0_modifiers, P.Src0VT:$src0,
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(Inst i32:$src0_modifiers, P.Src0VT:$src0,
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i32:$src1_modifiers, P.Src1VT:$src1,
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i32:$src1_modifiers, P.Src1VT:$src1,
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i32:$src2_modifiers, P.Src2VT:$src2,
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i32:$src2_modifiers, P.Src2VT:$src2,
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i32:$clamp,
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i1:$clamp,
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i32:$omod)>;
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i32:$omod)>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -39,7 +39,7 @@ define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double>
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; FUNC-LABEL: @fneg_free_f64
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; FUNC-LABEL: @fneg_free_f64
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; FIXME: Unnecessary copy to VGPRs
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; FIXME: Unnecessary copy to VGPRs
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; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]}}, 0, 0
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; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]$}}
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define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
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define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%bc = bitcast i64 %in to double
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%fsub = fsub double 0.0, %bc
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%fsub = fsub double 0.0, %bc
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@ -48,7 +48,7 @@ define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %i
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; R600: -KC0[2].Z
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; R600: -KC0[2].Z
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; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
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; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
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; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]}}, 0, 0
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; SI: V_SUB_F32_e64 v{{[0-9]}}, 0.0, s{{[0-9]+$}}
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define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
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define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%bc = bitcast i32 %in to float
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%fsub = fsub float 0.0, %bc
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%fsub = fsub float 0.0, %bc
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@ -27,7 +27,7 @@ define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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; SI: V_RCP_F32_e32 [[INVY:v[0-9]+]], [[Y]]
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; SI: V_RCP_F32_e32 [[INVY:v[0-9]+]], [[Y]]
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||||||
; SI: V_MUL_F32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
|
; SI: V_MUL_F32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
|
||||||
; SI: V_TRUNC_F32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
|
; SI: V_TRUNC_F32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
|
||||||
; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]],
|
; SI: V_MAD_F32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
|
||||||
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
||||||
; SI: S_ENDPGM
|
; SI: S_ENDPGM
|
||||||
define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
|
define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
|
||||||
|
@ -104,7 +104,7 @@ define void @store_literal_imm_f32(float addrspace(1)* %out) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_0.0_f32
|
; CHECK-LABEL: @add_inline_imm_0.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, 0.0
|
%y = fadd float %x, 0.0
|
||||||
@ -114,7 +114,7 @@ define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_0.5_f32
|
; CHECK-LABEL: @add_inline_imm_0.5_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, 0.5
|
%y = fadd float %x, 0.5
|
||||||
@ -124,7 +124,7 @@ define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_neg_0.5_f32
|
; CHECK-LABEL: @add_inline_imm_neg_0.5_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, -0.5
|
%y = fadd float %x, -0.5
|
||||||
@ -134,7 +134,7 @@ define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_1.0_f32
|
; CHECK-LABEL: @add_inline_imm_1.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, 1.0
|
%y = fadd float %x, 1.0
|
||||||
@ -144,7 +144,7 @@ define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_neg_1.0_f32
|
; CHECK-LABEL: @add_inline_imm_neg_1.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, -1.0
|
%y = fadd float %x, -1.0
|
||||||
@ -154,7 +154,7 @@ define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_2.0_f32
|
; CHECK-LABEL: @add_inline_imm_2.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, 2.0
|
%y = fadd float %x, 2.0
|
||||||
@ -164,7 +164,7 @@ define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_neg_2.0_f32
|
; CHECK-LABEL: @add_inline_imm_neg_2.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, -2.0
|
%y = fadd float %x, -2.0
|
||||||
@ -174,7 +174,7 @@ define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_4.0_f32
|
; CHECK-LABEL: @add_inline_imm_4.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, 4.0
|
%y = fadd float %x, 4.0
|
||||||
@ -184,7 +184,7 @@ define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
|
|||||||
|
|
||||||
; CHECK-LABEL: @add_inline_imm_neg_4.0_f32
|
; CHECK-LABEL: @add_inline_imm_neg_4.0_f32
|
||||||
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
|
||||||
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0,
|
; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0{{$}}
|
||||||
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
|
||||||
define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
|
define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
|
||||||
%y = fadd float %x, -4.0
|
%y = fadd float %x, -4.0
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s
|
||||||
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
||||||
|
|
||||||
declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
|
declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone
|
||||||
@ -6,7 +6,7 @@ declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone
|
|||||||
|
|
||||||
; FUNC-LABEL: @clamp_0_1_f32
|
; FUNC-LABEL: @clamp_0_1_f32
|
||||||
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
|
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
|
||||||
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]], 1, 0
|
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
|
||||||
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
||||||
; SI: S_ENDPGM
|
; SI: S_ENDPGM
|
||||||
|
|
||||||
@ -19,7 +19,7 @@ define void @clamp_0_1_f32(float addrspace(1)* %out, float %src) nounwind {
|
|||||||
|
|
||||||
; FUNC-LABEL: @clamp_0_1_amdil_legacy_f32
|
; FUNC-LABEL: @clamp_0_1_amdil_legacy_f32
|
||||||
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
|
; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
|
||||||
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]], 1, 0
|
; SI: V_ADD_F32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
|
||||||
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
; SI: BUFFER_STORE_DWORD [[RESULT]]
|
||||||
define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
|
define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
|
||||||
%clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
|
%clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
|
||||||
|
Loading…
Reference in New Issue
Block a user