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Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the scheduler to avoid clumping large groups of loads or stores too densely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62291 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -55,7 +55,10 @@ public:
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// instruction stream.
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/// instruction stream.
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virtual void EmitNoop() {}
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virtual void EmitNoop() {
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// Default implementation: count it as a cycle.
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AdvanceCycle();
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}
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};
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};
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}
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}
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@ -27,6 +27,7 @@
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -36,6 +37,7 @@
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#include <map>
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#include <map>
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using namespace llvm;
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using namespace llvm;
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STATISTIC(NumNoops, "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static cl::opt<bool>
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static cl::opt<bool>
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@ -43,6 +45,11 @@ EnableAntiDepBreaking("break-anti-dependencies",
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cl::desc("Break post-RA scheduling anti-dependencies"),
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cl::desc("Break post-RA scheduling anti-dependencies"),
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cl::init(true), cl::Hidden);
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnablePostRAHazardAvoidance("avoid-hazards",
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cl::desc("Enable simple hazard-avoidance"),
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cl::init(true), cl::Hidden);
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namespace {
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namespace {
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class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
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class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
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public:
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public:
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@ -84,12 +91,21 @@ namespace {
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/// because they may not be safe to break.
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/// because they may not be safe to break.
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const BitVector AllocatableSet;
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const BitVector AllocatableSet;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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public:
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public:
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SchedulePostRATDList(MachineFunction &MF,
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SchedulePostRATDList(MachineFunction &MF,
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const MachineLoopInfo &MLI,
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const MachineLoopInfo &MLI,
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const MachineDominatorTree &MDT)
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const MachineDominatorTree &MDT,
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ScheduleHazardRecognizer *HR)
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
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AllocatableSet(TRI->getAllocatableSet(MF)) {}
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AllocatableSet(TRI->getAllocatableSet(MF)),
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HazardRec(HR) {}
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~SchedulePostRATDList() {
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delete HazardRec;
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}
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void Schedule();
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void Schedule();
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@ -99,6 +115,62 @@ namespace {
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void ListScheduleTopDown();
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void ListScheduleTopDown();
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bool BreakAntiDependencies();
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bool BreakAntiDependencies();
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};
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};
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/// SimpleHazardRecognizer - A *very* simple hazard recognizer. It uses
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/// a coarse classification and attempts to avoid that instructions of
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/// a given class aren't grouped too densely together.
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class SimpleHazardRecognizer : public ScheduleHazardRecognizer {
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/// Class - A simple classification for SUnits.
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enum Class {
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Other, Load, Store
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};
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/// Window - The Class values of the most recently issued
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/// instructions.
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Class Window[8];
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/// getClass - Classify the given SUnit.
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Class getClass(const SUnit *SU) {
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const MachineInstr *MI = SU->getInstr();
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad())
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return Load;
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if (TID.mayStore())
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return Store;
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return Other;
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}
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/// Step - Rotate the existing entries in Window and insert the
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/// given class value in position as the most recent.
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void Step(Class C) {
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std::copy(Window+1, array_endof(Window), Window);
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Window[array_lengthof(Window)-1] = C;
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}
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public:
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SimpleHazardRecognizer() : Window() {}
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virtual HazardType getHazardType(SUnit *SU) {
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Class C = getClass(SU);
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if (C == Other)
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return NoHazard;
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unsigned Score = 0;
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for (int i = 0; i != array_lengthof(Window); ++i)
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if (Window[i] == C)
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Score += i + 1;
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if (Score > array_lengthof(Window) * 2)
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return Hazard;
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return NoHazard;
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}
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virtual void EmitInstruction(SUnit *SU) {
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Step(getClass(SU));
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}
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virtual void AdvanceCycle() {
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Step(Other);
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}
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};
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}
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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@ -106,8 +178,11 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
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new SimpleHazardRecognizer :
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new ScheduleHazardRecognizer();
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SchedulePostRATDList Scheduler(Fn, MLI, MDT);
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
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// Loop over all of the basic blocks
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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@ -634,6 +709,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
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// While Available queue is not empty, grab the node with the highest
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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Sequence.reserve(SUnits.size());
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Sequence.reserve(SUnits.size());
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while (!AvailableQueue.empty() || !PendingQueue.empty()) {
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while (!AvailableQueue.empty() || !PendingQueue.empty()) {
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// Check to see if any of the pending instructions are ready to issue. If
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// Check to see if any of the pending instructions are ready to issue. If
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@ -650,28 +726,63 @@ void SchedulePostRATDList::ListScheduleTopDown() {
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MinDepth = PendingQueue[i]->getDepth();
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MinDepth = PendingQueue[i]->getDepth();
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}
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}
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// If there are no instructions available, don't try to issue anything.
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// If there are no instructions available, don't try to issue anything, and
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// don't advance the hazard recognizer.
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if (AvailableQueue.empty()) {
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if (AvailableQueue.empty()) {
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CurCycle = MinDepth != ~0u ? MinDepth : CurCycle + 1;
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CurCycle = MinDepth != ~0u ? MinDepth : CurCycle + 1;
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continue;
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continue;
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}
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}
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SUnit *FoundSUnit = AvailableQueue.pop();
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SUnit *FoundSUnit = 0;
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bool HasNoopHazards = false;
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while (!AvailableQueue.empty()) {
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SUnit *CurSUnit = AvailableQueue.pop();
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ScheduleHazardRecognizer::HazardType HT =
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HazardRec->getHazardType(CurSUnit);
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if (HT == ScheduleHazardRecognizer::NoHazard) {
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FoundSUnit = CurSUnit;
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break;
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}
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// Remember if this is a noop hazard.
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HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
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NotReady.push_back(CurSUnit);
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}
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// Add the nodes that aren't ready back onto the available list.
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if (!NotReady.empty()) {
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AvailableQueue.push_all(NotReady);
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NotReady.clear();
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}
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// If we found a node to schedule, do it now.
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// If we found a node to schedule, do it now.
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if (FoundSUnit) {
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if (FoundSUnit) {
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ScheduleNodeTopDown(FoundSUnit, CurCycle);
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ScheduleNodeTopDown(FoundSUnit, CurCycle);
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HazardRec->EmitInstruction(FoundSUnit);
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// If this is a pseudo-op node, we don't want to increment the current
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// If this is a pseudo-op node, we don't want to increment the current
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// cycle.
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// cycle.
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if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
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if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
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++CurCycle;
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++CurCycle;
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} else {
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} else if (!HasNoopHazards) {
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// Otherwise, we have a pipeline stall, but no other problem, just advance
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// Otherwise, we have a pipeline stall, but no other problem, just advance
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// the current cycle and try again.
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// the current cycle and try again.
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DOUT << "*** Advancing cycle, no work to do\n";
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DOUT << "*** Advancing cycle, no work to do\n";
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HazardRec->AdvanceCycle();
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++NumStalls;
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++NumStalls;
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++CurCycle;
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++CurCycle;
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} else {
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// Otherwise, we have no instructions to issue and we have instructions
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// that will fault if we don't do this right. This is the case for
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// processors without pipeline interlocks and other cases.
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DOUT << "*** Emitting noop\n";
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HazardRec->EmitNoop();
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Sequence.push_back(0); // NULL here means noop
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++NumNoops;
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++CurCycle;
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}
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}
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}
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}
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@ -234,7 +234,7 @@ void ScheduleDAGList::ListScheduleTopDown() {
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// processors without pipeline interlocks and other cases.
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// processors without pipeline interlocks and other cases.
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DOUT << "*** Emitting noop\n";
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DOUT << "*** Emitting noop\n";
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HazardRec->EmitNoop();
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HazardRec->EmitNoop();
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Sequence.push_back(0); // NULL SUnit* -> noop
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Sequence.push_back(0); // NULL here means noop
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++NumNoops;
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++NumNoops;
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++CurCycle;
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++CurCycle;
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}
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}
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@ -302,7 +302,3 @@ void PPCHazardRecognizer970::AdvanceCycle() {
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if (NumIssued == 5)
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if (NumIssued == 5)
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EndDispatchGroup();
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EndDispatchGroup();
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}
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}
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void PPCHazardRecognizer970::EmitNoop() {
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AdvanceCycle();
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}
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@ -51,7 +51,6 @@ public:
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virtual HazardType getHazardType(SUnit *SU);
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virtual HazardType getHazardType(SUnit *SU);
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virtual void EmitInstruction(SUnit *SU);
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void AdvanceCycle();
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virtual void EmitNoop();
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private:
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private:
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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/// EndDispatchGroup - Called when we are finishing a new dispatch group.
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