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https://github.com/c64scene-ar/llvm-6502.git
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In preparation for replacing the whole subtarget on the target machine,
have target lowering take the subtarget explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213426 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -118,8 +118,9 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
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{"truncf", "__mips16_call_stub_sf_1"},
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};
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Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI)
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: MipsTargetLowering(TM, STI) {
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// Set up the register classes
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addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
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@ -150,8 +151,9 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
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}
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const MipsTargetLowering *
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llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
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return new Mips16TargetLowering(TM);
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llvm::createMips16TargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI) {
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return new Mips16TargetLowering(TM, STI);
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}
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bool
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@ -19,7 +19,8 @@
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namespace llvm {
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class Mips16TargetLowering : public MipsTargetLowering {
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public:
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explicit Mips16TargetLowering(MipsTargetMachine &TM);
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explicit Mips16TargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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bool *Fast) const override;
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@ -208,9 +208,9 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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: TargetLowering(TM, new MipsTargetObjectFile()),
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Subtarget(TM.getSubtarget<MipsSubtarget>()) {
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MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI)
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: TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) {
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setBooleanContents(ZeroOrOneBooleanContent);
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@ -403,11 +403,12 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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isMicroMips = Subtarget.inMicroMipsMode();
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}
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const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
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if (TM.getSubtargetImpl()->inMips16Mode())
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return llvm::createMips16TargetLowering(TM);
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const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM,
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const MipsSubtarget &STI) {
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if (STI.inMips16Mode())
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return llvm::createMips16TargetLowering(TM, STI);
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return llvm::createMipsSETargetLowering(TM);
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return llvm::createMipsSETargetLowering(TM, STI);
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}
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// Create a fast isel object.
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@ -214,9 +214,11 @@ namespace llvm {
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class MipsTargetLowering : public TargetLowering {
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bool isMicroMips;
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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explicit MipsTargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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static const MipsTargetLowering *create(MipsTargetMachine &TM);
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static const MipsTargetLowering *create(MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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@ -611,8 +613,10 @@ namespace llvm {
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};
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/// Create MipsTargetLowering objects.
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const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
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const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
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const MipsTargetLowering *
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createMips16TargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
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const MipsTargetLowering *
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createMipsSETargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
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namespace Mips {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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@ -34,8 +34,9 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
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"stores to their single precision "
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"counterparts"));
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI)
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: MipsTargetLowering(TM, STI) {
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// Set up the register classes
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addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
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@ -226,8 +227,9 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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}
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const MipsTargetLowering *
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llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
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return new MipsSETargetLowering(TM);
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llvm::createMipsSETargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI) {
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return new MipsSETargetLowering(TM, STI);
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}
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const TargetRegisterClass *
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@ -20,7 +20,8 @@
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namespace llvm {
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class MipsSETargetLowering : public MipsTargetLowering {
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public:
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explicit MipsSETargetLowering(MipsTargetMachine &TM);
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explicit MipsSETargetLowering(MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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/// \brief Enable MSA support for the given integer type and Register
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/// class.
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@ -117,7 +117,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
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TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),
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FrameLowering(MipsFrameLowering::create(*TM, *this)),
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TLInfo(MipsTargetLowering::create(*TM)) {
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TLInfo(MipsTargetLowering::create(*TM, *this)) {
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PreviousInMips16Mode = InMips16Mode;
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@ -256,7 +256,7 @@ void MipsSubtarget::setHelperClassesMips16() {
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if (!InstrInfo16) {
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InstrInfo.reset(MipsInstrInfo::create(*this));
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FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
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TLInfo.reset(MipsTargetLowering::create(*TM));
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TLInfo.reset(MipsTargetLowering::create(*TM, *this));
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} else {
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InstrInfo16.swap(InstrInfo);
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FrameLowering16.swap(FrameLowering);
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@ -274,7 +274,7 @@ void MipsSubtarget::setHelperClassesMipsSE() {
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if (!InstrInfoSE) {
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InstrInfo.reset(MipsInstrInfo::create(*this));
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FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
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TLInfo.reset(MipsTargetLowering::create(*TM));
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TLInfo.reset(MipsTargetLowering::create(*TM, *this));
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} else {
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InstrInfoSE.swap(InstrInfo);
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FrameLoweringSE.swap(FrameLowering);
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