In preparation for replacing the whole subtarget on the target machine,

have target lowering take the subtarget explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213426 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-07-18 23:25:04 +00:00
parent a002a91ad8
commit 286fbd19f3
7 changed files with 35 additions and 24 deletions

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@ -118,8 +118,9 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
{"truncf", "__mips16_call_stub_sf_1"},
};
Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
: MipsTargetLowering(TM) {
Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI)
: MipsTargetLowering(TM, STI) {
// Set up the register classes
addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
@ -150,8 +151,9 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
}
const MipsTargetLowering *
llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
return new Mips16TargetLowering(TM);
llvm::createMips16TargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI) {
return new Mips16TargetLowering(TM, STI);
}
bool

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@ -19,7 +19,8 @@
namespace llvm {
class Mips16TargetLowering : public MipsTargetLowering {
public:
explicit Mips16TargetLowering(MipsTargetMachine &TM);
explicit Mips16TargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI);
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const override;

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@ -208,9 +208,9 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
: TargetLowering(TM, new MipsTargetObjectFile()),
Subtarget(TM.getSubtarget<MipsSubtarget>()) {
MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI)
: TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
@ -403,11 +403,12 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
isMicroMips = Subtarget.inMicroMipsMode();
}
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
if (TM.getSubtargetImpl()->inMips16Mode())
return llvm::createMips16TargetLowering(TM);
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM,
const MipsSubtarget &STI) {
if (STI.inMips16Mode())
return llvm::createMips16TargetLowering(TM, STI);
return llvm::createMipsSETargetLowering(TM);
return llvm::createMipsSETargetLowering(TM, STI);
}
// Create a fast isel object.

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@ -214,9 +214,11 @@ namespace llvm {
class MipsTargetLowering : public TargetLowering {
bool isMicroMips;
public:
explicit MipsTargetLowering(MipsTargetMachine &TM);
explicit MipsTargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI);
static const MipsTargetLowering *create(MipsTargetMachine &TM);
static const MipsTargetLowering *create(MipsTargetMachine &TM,
const MipsSubtarget &STI);
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
@ -611,8 +613,10 @@ namespace llvm {
};
/// Create MipsTargetLowering objects.
const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
const MipsTargetLowering *
createMips16TargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
const MipsTargetLowering *
createMipsSETargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
namespace Mips {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

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@ -34,8 +34,9 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
"stores to their single precision "
"counterparts"));
MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
: MipsTargetLowering(TM) {
MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI)
: MipsTargetLowering(TM, STI) {
// Set up the register classes
addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
@ -226,8 +227,9 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
}
const MipsTargetLowering *
llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
return new MipsSETargetLowering(TM);
llvm::createMipsSETargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI) {
return new MipsSETargetLowering(TM, STI);
}
const TargetRegisterClass *

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@ -20,7 +20,8 @@
namespace llvm {
class MipsSETargetLowering : public MipsTargetLowering {
public:
explicit MipsSETargetLowering(MipsTargetMachine &TM);
explicit MipsSETargetLowering(MipsTargetMachine &TM,
const MipsSubtarget &STI);
/// \brief Enable MSA support for the given integer type and Register
/// class.

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@ -117,7 +117,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),
FrameLowering(MipsFrameLowering::create(*TM, *this)),
TLInfo(MipsTargetLowering::create(*TM)) {
TLInfo(MipsTargetLowering::create(*TM, *this)) {
PreviousInMips16Mode = InMips16Mode;
@ -256,7 +256,7 @@ void MipsSubtarget::setHelperClassesMips16() {
if (!InstrInfo16) {
InstrInfo.reset(MipsInstrInfo::create(*this));
FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
TLInfo.reset(MipsTargetLowering::create(*TM));
TLInfo.reset(MipsTargetLowering::create(*TM, *this));
} else {
InstrInfo16.swap(InstrInfo);
FrameLowering16.swap(FrameLowering);
@ -274,7 +274,7 @@ void MipsSubtarget::setHelperClassesMipsSE() {
if (!InstrInfoSE) {
InstrInfo.reset(MipsInstrInfo::create(*this));
FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
TLInfo.reset(MipsTargetLowering::create(*TM));
TLInfo.reset(MipsTargetLowering::create(*TM, *this));
} else {
InstrInfoSE.swap(InstrInfo);
FrameLoweringSE.swap(FrameLowering);