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ADd support for undef and unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17050 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -237,9 +237,10 @@ namespace {
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// Visitation methods for various instructions. These methods simply emit
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// Visitation methods for various instructions. These methods simply emit
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// fixed PowerPC code for each instruction.
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// fixed PowerPC code for each instruction.
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// Control flow operators
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// Control flow operators.
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void visitReturnInst(ReturnInst &RI);
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void visitReturnInst(ReturnInst &RI);
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void visitBranchInst(BranchInst &BI);
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void visitBranchInst(BranchInst &BI);
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void visitUnreachableInst(UnreachableInst &UI) {}
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struct ValueRecord {
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struct ValueRecord {
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Value *Val;
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Value *Val;
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@ -575,6 +576,10 @@ void PPC32ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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MachineBasicBlock::iterator IP,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (isa<UndefValue>(C)) {
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BuildMI(*MBB, IP, PPC::IMPLICIT_DEF, 0, R);
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return;
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}
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if (C->getType()->isIntegral()) {
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if (C->getType()->isIntegral()) {
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unsigned Class = getClassB(C->getType());
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unsigned Class = getClassB(C->getType());
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@ -2117,9 +2122,8 @@ void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
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// xor X, -1 -> not X
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// xor X, -1 -> not X
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if (Opcode == 4) {
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if (Opcode == 4) {
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ConstantSInt *CSI = dyn_cast<ConstantSInt>(Op1);
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ConstantInt *CI = dyn_cast<ConstantSInt>(Op1);
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ConstantUInt *CUI = dyn_cast<ConstantUInt>(Op1);
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if (CI && CI->isAllOnesValue()) {
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if ((CSI && CSI->isAllOnesValue()) || (CUI && CUI->isAllOnesValue())) {
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BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
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BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
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return;
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return;
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}
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}
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