Add vmfunc instruction to X86 assembler and disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-02-19 01:39:49 +00:00
parent 507329912a
commit 28a713b20a
9 changed files with 48 additions and 28 deletions

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@ -233,8 +233,9 @@ namespace X86II {
MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36,
MRM_C8 = 37, MRM_C9 = 38, MRM_E8 = 39, MRM_F0 = 40, MRM_C8 = 37, MRM_C9 = 38, MRM_E8 = 39, MRM_F0 = 40,
MRM_F8 = 41, MRM_F9 = 42, MRM_D0 = 45, MRM_D1 = 46, MRM_F8 = 41, MRM_F9 = 42, MRM_D0 = 45, MRM_D1 = 46,
MRM_D8 = 47, MRM_D9 = 48, MRM_DA = 49, MRM_DB = 50, MRM_D4 = 47, MRM_D8 = 48, MRM_D9 = 49, MRM_DA = 50,
MRM_DC = 51, MRM_DD = 52, MRM_DE = 53, MRM_DF = 54, MRM_DB = 51, MRM_DC = 52, MRM_DD = 53, MRM_DE = 54,
MRM_DF = 55,
/// RawFrmImm8 - This is used for the ENTER instruction, which has two /// RawFrmImm8 - This is used for the ENTER instruction, which has two
/// immediates, the first of which is a 16-bit immediate (specified by /// immediates, the first of which is a 16-bit immediate (specified by
@ -534,10 +535,11 @@ namespace X86II {
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_E8: case X86II::MRM_F0:
case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_F8: case X86II::MRM_F9:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_D4: case X86II::MRM_D8:
case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_D9: case X86II::MRM_DA:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_DF:
return -1; return -1;
} }
} }

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@ -1062,12 +1062,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C3: case X86II::MRM_C4:
case X86II::MRM_C8: case X86II::MRM_C9: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_D4: case X86II::MRM_D8:
case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_D9: case X86II::MRM_DA:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DB: case X86II::MRM_DC:
case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_DF: case X86II::MRM_E8:
case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_F0: case X86II::MRM_F8:
case X86II::MRM_F9:
EmitByte(BaseOpcode, CurByte, OS); EmitByte(BaseOpcode, CurByte, OS);
unsigned char MRM; unsigned char MRM;
@ -1081,6 +1082,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_C9: MRM = 0xC9; break; case X86II::MRM_C9: MRM = 0xC9; break;
case X86II::MRM_D0: MRM = 0xD0; break; case X86II::MRM_D0: MRM = 0xD0; break;
case X86II::MRM_D1: MRM = 0xD1; break; case X86II::MRM_D1: MRM = 0xD1; break;
case X86II::MRM_D4: MRM = 0xD4; break;
case X86II::MRM_D8: MRM = 0xD8; break; case X86II::MRM_D8: MRM = 0xD8; break;
case X86II::MRM_D9: MRM = 0xD9; break; case X86II::MRM_D9: MRM = 0xD9; break;
case X86II::MRM_DA: MRM = 0xDA; break; case X86II::MRM_DA: MRM = 0xDA; break;

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@ -43,14 +43,15 @@ def RawFrmImm8 : Format<43>;
def RawFrmImm16 : Format<44>; def RawFrmImm16 : Format<44>;
def MRM_D0 : Format<45>; def MRM_D0 : Format<45>;
def MRM_D1 : Format<46>; def MRM_D1 : Format<46>;
def MRM_D8 : Format<47>; def MRM_D4 : Format<47>;
def MRM_D9 : Format<48>; def MRM_D8 : Format<48>;
def MRM_DA : Format<49>; def MRM_D9 : Format<49>;
def MRM_DB : Format<50>; def MRM_DA : Format<50>;
def MRM_DC : Format<51>; def MRM_DB : Format<51>;
def MRM_DD : Format<52>; def MRM_DC : Format<52>;
def MRM_DE : Format<53>; def MRM_DD : Format<53>;
def MRM_DF : Format<54>; def MRM_DE : Format<54>;
def MRM_DF : Format<55>;
// ImmType - This specifies the immediate type used by an instruction. This is // ImmType - This specifies the immediate type used by an instruction. This is
// part of the ad-hoc solution used to emit machine instruction encodings by our // part of the ad-hoc solution used to emit machine instruction encodings by our

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@ -33,6 +33,8 @@ def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
"vmclear\t$vmcs", []>, OpSize, TB; "vmclear\t$vmcs", []>, OpSize, TB;
// OF 01 D4
def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
// 0F 01 C2 // 0F 01 C2
def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB; def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
// 0F 01 C3 // 0F 01 C3

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@ -28,6 +28,9 @@
# CHECK: vmcall # CHECK: vmcall
0x0f 0x01 0xc1 0x0f 0x01 0xc1
# CHECK: vmfunc
0x0f 0x01 0xd4
# CHECK: vmlaunch # CHECK: vmlaunch
0x0f 0x01 0xc2 0x0f 0x01 0xc2

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@ -63,6 +63,9 @@
# CHECK: vmcall # CHECK: vmcall
0x0f 0x01 0xc1 0x0f 0x01 0xc1
# CHECK: vmfunc
0x0f 0x01 0xd4
# CHECK: vmlaunch # CHECK: vmlaunch
0x0f 0x01 0xc2 0x0f 0x01 0xc2

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@ -18408,6 +18408,9 @@
// CHECK: vmcall // CHECK: vmcall
vmcall vmcall
// CHECK: vmfunc
vmfunc
// CHECK: vmclear 3735928559(%ebx,%ecx,8) // CHECK: vmclear 3735928559(%ebx,%ecx,8)
vmclear 0xdeadbeef(%ebx,%ecx,8) vmclear 0xdeadbeef(%ebx,%ecx,8)

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@ -28,6 +28,9 @@
vmcall vmcall
// CHECK: vmcall // CHECK: vmcall
// CHECK: encoding: [0x0f,0x01,0xc1] // CHECK: encoding: [0x0f,0x01,0xc1]
vmfunc
// CHECK: vmfunc
// CHECK: encoding: [0x0f,0x01,0xd4]
vmlaunch vmlaunch
// CHECK: vmlaunch // CHECK: vmlaunch
// CHECK: encoding: [0x0f,0x01,0xc2] // CHECK: encoding: [0x0f,0x01,0xc2]

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@ -37,14 +37,15 @@ using namespace llvm;
MAP(F9, 42) \ MAP(F9, 42) \
MAP(D0, 45) \ MAP(D0, 45) \
MAP(D1, 46) \ MAP(D1, 46) \
MAP(D8, 47) \ MAP(D4, 47) \
MAP(D9, 48) \ MAP(D8, 48) \
MAP(DA, 49) \ MAP(D9, 49) \
MAP(DB, 50) \ MAP(DA, 50) \
MAP(DC, 51) \ MAP(DB, 51) \
MAP(DD, 52) \ MAP(DC, 52) \
MAP(DE, 53) \ MAP(DD, 53) \
MAP(DF, 54) MAP(DE, 54) \
MAP(DF, 55)
// A clone of X86 since we can't depend on something that is generated. // A clone of X86 since we can't depend on something that is generated.
namespace X86Local { namespace X86Local {