From 28b1a0b5323eb6953f40c28b4a2b02c6602d49ac Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 19 Mar 2006 05:33:30 +0000 Subject: [PATCH] notes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26856 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/README.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index c4cf3035437..42a644c1f33 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -506,6 +506,7 @@ Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector registers, to generate better spill code. ===-------------------------------------------------------------------------=== + int foo(int N, int ***W, int **TK, int X) { int t, i; @@ -518,5 +519,20 @@ int foo(int N, int ***W, int **TK, int X) { We generate relatively atrocious code for this loop compared to gcc. +===-------------------------------------------------------------------------=== +Altivec support. The first should be a single lvx from the constant pool, the +second should be a xor/stvx: + +void foo(void) { + int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +} + +#include +void foo(void) { + int x[8] __attribute__((aligned(128))); + memset (x, 0, sizeof (x)); + bar (x); +}