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- Switch X86-64 JIT to large code size model.
- Re-enable some codegen niceties for X86-64 static relocation model codegen. - Clean ups, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32238 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -229,41 +229,6 @@ list so it will be passed in register:
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//===---------------------------------------------------------------------===//
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For this:
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extern int dst[];
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extern int* ptr;
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void test(void) {
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ptr = dst;
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}
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We generate this code for static relocation model:
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_test:
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leaq _dst(%rip), %rax
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movq %rax, _ptr(%rip)
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ret
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If we are in small code model, they we can treat _dst as a 32-bit constant.
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movq $_dst, _ptr(%rip)
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Note, however, we should continue to use RIP relative addressing mode as much as
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possible. The above is actually one byte shorter than
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movq $_dst, _ptr
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A better example is the code from PR1018. We are generating:
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leaq xcalloc2(%rip), %rax
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movq %rax, 8(%rsp)
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when we should be generating:
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movq $xcalloc2, 8(%rsp)
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The reason the better codegen isn't done now is support for static small
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code model in JIT mode. The JIT cannot ensure that all GV's are placed in the
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lower 4G so we are not treating GV labels as 32-bit values.
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//===---------------------------------------------------------------------===//
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Right now the asm printer assumes GlobalAddress are accessed via RIP relative
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addressing. Therefore, it is not possible to generate this:
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movabsq $__ZTV10polynomialIdE+16, %rax
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@ -156,7 +156,7 @@ bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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}
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void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier) {
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const char *Modifier, bool NotRIPRel) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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@ -192,7 +192,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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if (X86PICStyle == PICStyle::Stub &&
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TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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if (isMemOp && Subtarget->is64Bit())
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if (isMemOp && Subtarget->is64Bit() && !NotRIPRel)
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O << "(%rip)";
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return;
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}
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@ -210,7 +210,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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else if (Offset < 0)
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O << Offset;
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if (isMemOp && Subtarget->is64Bit())
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if (isMemOp && Subtarget->is64Bit() && !NotRIPRel)
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O << "(%rip)";
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return;
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}
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@ -267,8 +267,12 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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if (isMemOp && Subtarget->is64Bit()) {
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if (isExt && TM.getRelocationModel() != Reloc::Static)
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O << "@GOTPCREL";
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O << "(%rip)";
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O << "@GOTPCREL(%rip)";
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else if (!NotRIPRel)
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// Use rip when possible to reduce code size, except when index or
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// base register are also part of the address. e.g.
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// foo(%rip)(%rcx,%rax,4) is not legal
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O << "(%rip)";
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}
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return;
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@ -329,10 +333,11 @@ void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
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return;
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}
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bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
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if (DispSpec.isGlobalAddress() ||
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DispSpec.isConstantPoolIndex() ||
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DispSpec.isJumpTableIndex()) {
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printOperand(MI, Op+3, "mem");
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printOperand(MI, Op+3, "mem", NotRIPRel);
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} else {
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int DispVal = DispSpec.getImmedValue();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
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@ -35,7 +35,7 @@ struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
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// These methods are used by the tablegen'erated instruction printer.
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void printOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier = 0);
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const char *Modifier = 0, bool NotRIPRel = false);
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void printi8mem(const MachineInstr *MI, unsigned OpNo) {
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printMemReference(MI, OpNo);
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}
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@ -595,44 +595,43 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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// Under X86-64 non-small code model, GV (and friends) are 64-bits.
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if (is64Bit && TM.getCodeModel() != CodeModel::Small)
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break;
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if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
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break;
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// If value is available in a register both base and index components have
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// been picked, we can't fit the result available in the register in the
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// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
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if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
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// For X86-64 PIC code, only allow GV / CP + displacement so we can use
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// RIP relative addressing mode.
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if (is64Bit &&
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(AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
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AM.BaseType == X86ISelAddressMode::FrameIndexBase))
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break;
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if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
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if (AM.CP == 0) {
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bool isStatic = TM.getRelocationModel() == Reloc::Static;
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SDOperand N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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GlobalValue *GV = G->getGlobal();
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bool isAbs32 = !is64Bit ||
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(isStatic && !(GV->isExternal() || GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage()));
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if (isAbs32 || isRoot) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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AM.isRIPRel = !isAbs32;
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return false;
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}
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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if (!is64Bit || isStatic || isRoot) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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AM.isRIPRel = is64Bit;
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AM.isRIPRel = !isStatic;
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return false;
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}
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} else if (GlobalAddressSDNode *G =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
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if (AM.GV == 0) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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AM.isRIPRel = is64Bit;
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return false;
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}
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} else if (isRoot && is64Bit) {
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if (ExternalSymbolSDNode *S =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(0))) {
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} else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
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if (isStatic || isRoot) {
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AM.ES = S->getSymbol();
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AM.isRIPRel = true;
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AM.isRIPRel = !isStatic;
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return false;
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} else if (JumpTableSDNode *J =
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dyn_cast<JumpTableSDNode>(N.getOperand(0))) {
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}
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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if (isStatic || isRoot) {
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AM.JT = J->getIndex();
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AM.isRIPRel = true;
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AM.isRIPRel = !isStatic;
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return false;
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}
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}
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@ -908,7 +907,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDOperand Op, SDOperand N,
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if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
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// For X86-64, we should always use lea to materialize RIP relative
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// addresses.
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if (Subtarget->is64Bit())
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if (Subtarget->is64Bit() && TM.getRelocationModel() != Reloc::Static)
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Complexity = 4;
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else
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Complexity += 2;
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@ -163,15 +163,16 @@ def MRMInitReg : Format<32>;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Predicate Definitions.
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def HasMMX : Predicate<"Subtarget->hasMMX()">;
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def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
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def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
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def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
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def FPStack : Predicate<"!Subtarget->hasSSE2()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
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def In64BitMode : Predicate<"Subtarget->is64Bit()">;
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def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
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def NotSmallCode :Predicate<"TM.getCodeModel() != CodeModel::Small">;
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def HasMMX : Predicate<"Subtarget->hasMMX()">;
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def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
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def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
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def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
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def FPStack : Predicate<"!Subtarget->hasSSE2()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
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def In64BitMode : Predicate<"Subtarget->is64Bit()">;
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def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
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def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
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def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
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//===----------------------------------------------------------------------===//
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// X86 specific pattern fragments.
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@ -1031,12 +1031,18 @@ def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
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/*
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def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tconstpool:$src)>,
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tjumptable:$src)>,
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tglobaladdr:$src)>, Requires<[SmallCode]>;
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(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
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Requires<[SmallCode, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, texternalsym:$src)>, Requires<[SmallCode]>;
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*/
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(MOV64mi32 addr:$dst, texternalsym:$src)>,
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Requires<[SmallCode, IsStatic]>;
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// Calls
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// Direct PC relative function call for small code model. 32-bit displacement
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@ -158,6 +158,9 @@ bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
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MachineCodeEmitter &MCE) {
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// FIXME: Move this to TargetJITInfo!
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setRelocationModel(Reloc::Static);
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// JIT cannot ensure globals are placed in the lower 4G of address.
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if (Subtarget.is64Bit())
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setCodeModel(CodeModel::Large);
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PM.add(createX86CodeEmitterPass(*this, MCE));
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return false;
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