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Interface of getByValTypeAlignment differed between

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generic & x86 versions; change generic to follow x86
and improve comments.  Add PPC version (not right
for non-Darwin.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2008-02-28 22:31:51 +00:00
parent 63b8c1f6f1
commit 28d08fdb9f
4 changed files with 21 additions and 3 deletions
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3
include/llvm/Target/TargetLowering.h
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@ -420,7 +420,8 @@ public:
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area.
/// function arguments in the caller parameter area. This is the actual
/// alignment, not its logarithm.
virtual unsigned getByValTypeAlignment(const Type *Ty) const;
/// getRegisterType - Return the type of registers that this ValueType will

5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -424,9 +424,10 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area.
/// function arguments in the caller parameter area. This is the actual
/// alignment, not its logarithm.
unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
return Log2_32(TD->getCallFrameTypeAlignment(Ty));
return TD->getCallFrameTypeAlignment(Ty);
}
SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table,

11
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -351,6 +351,17 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
computeRegisterProperties();
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area.
unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
TargetMachine &TM = getTargetMachine();
// Darwin passes everything on 4 byte boundary.
if (TM.getSubtarget<PPCSubtarget>().isDarwin())
return 4;
// FIXME Elf TBD
return 4;
}
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;

5
lib/Target/PowerPC/PPCISelLowering.h
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@ -268,6 +268,11 @@ namespace llvm {
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
/// function arguments in the caller parameter area. This is the actual
/// alignment, not its logarithm.
unsigned getByValTypeAlignment(const Type *Ty) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDOperand Op,