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ZERO_EXTEND operation is optimized for AVX.
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -14349,7 +14349,8 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
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static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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// (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
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// (and (i32 x86isd::setcc_carry), 1)
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// This eliminates the zext. This transformation is necessary because
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@ -14357,6 +14358,8 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
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DebugLoc dl = N->getDebugLoc();
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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EVT OpVT = N0.getValueType();
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if (N0.getOpcode() == ISD::AND &&
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N0.hasOneUse() &&
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N0.getOperand(0).hasOneUse()) {
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@ -14371,6 +14374,38 @@ static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
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N00.getOperand(0), N00.getOperand(1)),
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DAG.getConstant(1, VT));
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}
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// Optimize vectors in AVX mode:
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//
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// v8i16 -> v8i32
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// Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
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// Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
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// Concat upper and lower parts.
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//
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// v4i32 -> v4i64
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// Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
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// Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
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// Concat upper and lower parts.
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//
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if (Subtarget->hasAVX()) {
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if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
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((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
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SDValue ZeroVec = getZeroVector(OpVT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
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DAG, dl);
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SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
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SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
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EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
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VT.getVectorNumElements()/2);
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OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
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OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
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}
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}
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return SDValue();
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}
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@ -14558,7 +14593,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::FAND: return PerformFANDCombine(N, DAG);
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
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case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
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case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
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case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
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case X86ISD::SHUFP: // Handle all target specific shuffles
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case X86ISD::PALIGN:
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17
test/CodeGen/X86/avx-zext.ll
Executable file
17
test/CodeGen/X86/avx-zext.ll
Executable file
@ -0,0 +1,17 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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;CHECK: zext_8i16_to_8i32
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;CHECK: vpunpckhwd
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%B = zext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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;CHECK: zext_4i32_to_4i64
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;CHECK: vpunpckhdq
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%B = zext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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