From 2920d2b7b601d9dfcec783cb91316f35b6811be1 Mon Sep 17 00:00:00 2001 From: Mon P Wang Date: Tue, 15 Jul 2008 05:28:34 +0000 Subject: [PATCH] Fixed potential bug if the source and target of a bit convert have different alignment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53590 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 632653b624d..4b9236db467 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -7015,7 +7015,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // The input is a scalar or single-element vector. // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. - SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); + unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( + Op.getValueType().getTypeForMVT()); + SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); int FI = cast(Ptr.Val)->getIndex(); SDOperand St = DAG.getStore(DAG.getEntryNode(),