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Merging r214180:
------------------------------------------------------------------------ r214180 | sstankovic | 2014-07-29 15:39:24 +0100 (Tue, 29 Jul 2014) | 5 lines [mips] Don't use odd-numbered single precision registers for fastcc calling convention if -mno-odd-spreg is used. Differential Revision: http://reviews.llvm.org/D4682 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214304 91177308-0d34-0410-b5e6-96231b3b80d8
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Daniel Sanders
parent
dacdc7cf93
commit
29750a28c3
@ -203,8 +203,13 @@ def CC_Mips_FastCC : CallingConv<[
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CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
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// f32 arguments are passed in single-precision floating pointer registers.
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CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
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F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
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CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
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CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
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F14, F15, F16, F17, F18, F19]>>>,
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// Don't use odd numbered single-precision registers for -mno-odd-spreg.
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CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
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CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
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// Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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@ -203,6 +203,7 @@ public:
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bool isFPXX() const { return IsFPXX; }
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bool isFP64bit() const { return IsFP64bit; }
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bool useOddSPReg() const { return UseOddSPReg; }
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bool noOddSPReg() const { return !UseOddSPReg; }
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bool isNaN2008() const { return IsNaN2008bit; }
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bool isNotFP64bit() const { return !IsFP64bit; }
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bool isGP64bit() const { return IsGP64bit; }
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@ -1,6 +1,7 @@
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; RUN: llc < %s -march=mipsel | FileCheck %s
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; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu \
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; RUN: | FileCheck %s -check-prefix=CHECK-NACL
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg | FileCheck %s -check-prefix=NOODDSPREG
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@gi0 = external global i32
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@ -80,6 +81,8 @@
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@g15 = external global i32
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@g16 = external global i32
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@fa = common global [11 x float] zeroinitializer, align 4
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define void @caller0() nounwind {
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entry:
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; CHECK: caller0
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@ -264,3 +267,84 @@ entry:
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ret void
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}
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define void @caller2() {
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entry:
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; NOODDSPREG-LABEL: caller2
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; Check that first 10 arguments are passed in even float registers
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; f0, f2, ... , f18. Check that 11th argument is passed on stack.
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; NOODDSPREG-DAG: lw $[[R0:[0-9]+]], %got(fa)(${{[0-9]+|gp}})
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; NOODDSPREG-DAG: lwc1 $f0, 0($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f2, 4($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f4, 8($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f6, 12($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f8, 16($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f10, 20($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f12, 24($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f14, 28($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f16, 32($[[R0]])
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; NOODDSPREG-DAG: lwc1 $f18, 36($[[R0]])
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; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], 40($[[R0]])
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; NOODDSPREG-DAG: swc1 $[[F0]], 0($sp)
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%0 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 0), align 4
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%1 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 1), align 4
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%2 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 2), align 4
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%3 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 3), align 4
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%4 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 4), align 4
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%5 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 5), align 4
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%6 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 6), align 4
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%7 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 7), align 4
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%8 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 8), align 4
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%9 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 9), align 4
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%10 = load float* getelementptr ([11 x float]* @fa, i32 0, i32 10), align 4
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tail call fastcc void @callee2(float %0, float %1, float %2, float %3,
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float %4, float %5, float %6, float %7,
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float %8, float %9, float %10)
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ret void
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}
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define fastcc void @callee2(float %a0, float %a1, float %a2, float %a3,
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float %a4, float %a5, float %a6, float %a7,
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float %a8, float %a9, float %a10) {
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entry:
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; NOODDSPREG-LABEL: callee2
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; NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]]
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; Check that first 10 arguments are received in even float registers
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; f0, f2, ... , f18. Check that 11th argument is received on stack.
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; NOODDSPREG-DAG: lw $[[R0:[0-9]+]], %got(fa)(${{[0-9]+|gp}})
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; NOODDSPREG-DAG: swc1 $f0, 0($[[R0]])
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; NOODDSPREG-DAG: swc1 $f2, 4($[[R0]])
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; NOODDSPREG-DAG: swc1 $f4, 8($[[R0]])
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; NOODDSPREG-DAG: swc1 $f6, 12($[[R0]])
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; NOODDSPREG-DAG: swc1 $f8, 16($[[R0]])
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; NOODDSPREG-DAG: swc1 $f10, 20($[[R0]])
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; NOODDSPREG-DAG: swc1 $f12, 24($[[R0]])
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; NOODDSPREG-DAG: swc1 $f14, 28($[[R0]])
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; NOODDSPREG-DAG: swc1 $f16, 32($[[R0]])
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; NOODDSPREG-DAG: swc1 $f18, 36($[[R0]])
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; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
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; NOODDSPREG-DAG: swc1 $[[F0]], 40($[[R0]])
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store float %a0, float* getelementptr ([11 x float]* @fa, i32 0, i32 0), align 4
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store float %a1, float* getelementptr ([11 x float]* @fa, i32 0, i32 1), align 4
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store float %a2, float* getelementptr ([11 x float]* @fa, i32 0, i32 2), align 4
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store float %a3, float* getelementptr ([11 x float]* @fa, i32 0, i32 3), align 4
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store float %a4, float* getelementptr ([11 x float]* @fa, i32 0, i32 4), align 4
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store float %a5, float* getelementptr ([11 x float]* @fa, i32 0, i32 5), align 4
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store float %a6, float* getelementptr ([11 x float]* @fa, i32 0, i32 6), align 4
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store float %a7, float* getelementptr ([11 x float]* @fa, i32 0, i32 7), align 4
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store float %a8, float* getelementptr ([11 x float]* @fa, i32 0, i32 8), align 4
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store float %a9, float* getelementptr ([11 x float]* @fa, i32 0, i32 9), align 4
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store float %a10, float* getelementptr ([11 x float]* @fa, i32 0, i32 10), align 4
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ret void
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}
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