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Switch to ArrayRef<CodeGenRegisterClass*>.

Browse Source 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-09-29 22:28:37 +00:00
parent 27e0666725
commit 29f018cee6
8 changed files with 58 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -914,17 +914,17 @@ void AsmMatcherInfo::
BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
const std::vector<CodeGenRegister*> &Registers = const std::vector<CodeGenRegister*> &Registers =
Target.getRegBank().getRegisters(); Target.getRegBank().getRegisters();
const std::vector<CodeGenRegisterClass> &RegClassList = ArrayRef<CodeGenRegisterClass*> RegClassList =
Target.getRegisterClasses(); Target.getRegBank().getRegClasses();
// The register sets used for matching. // The register sets used for matching.
std::set< std::set<Record*> > RegisterSets; std::set< std::set<Record*> > RegisterSets;
// Gather the defined sets. // Gather the defined sets.
for (std::vector<CodeGenRegisterClass>::const_iterator it = for (ArrayRef<CodeGenRegisterClass*>::const_iterator it =
RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it)
RegisterSets.insert(std::set<Record*>(it->getOrder().begin(), RegisterSets.insert(std::set<Record*>(
it->getOrder().end())); (*it)->getOrder().begin(), (*it)->getOrder().end()));
// Add any required singleton sets. // Add any required singleton sets.
for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(),
@ -996,18 +996,19 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
} }
// Name the register classes which correspond to a user defined RegisterClass. // Name the register classes which correspond to a user defined RegisterClass.
for (std::vector<CodeGenRegisterClass>::const_iterator for (ArrayRef<CodeGenRegisterClass*>::const_iterator
it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) {
ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->getOrder().begin(), const CodeGenRegisterClass &RC = **it;
it->getOrder().end())]; ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(),
RC.getOrder().end())];
if (CI->ValueName.empty()) { if (CI->ValueName.empty()) {
CI->ClassName = it->getName(); CI->ClassName = RC.getName();
CI->Name = "MCK_" + it->getName(); CI->Name = "MCK_" + RC.getName();
CI->ValueName = it->getName(); CI->ValueName = RC.getName();
} else } else
CI->ValueName = CI->ValueName + "," + it->getName(); CI->ValueName = CI->ValueName + "," + RC.getName();
RegisterClassClasses.insert(std::make_pair(it->TheDef, CI)); RegisterClassClasses.insert(std::make_pair(RC.TheDef, CI));
} }
// Populate the map for individual registers. // Populate the map for individual registers.

8
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -703,8 +703,8 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
CodeGenTarget Target(Records); CodeGenTarget Target(Records);
// Enumerate the register classes. // Enumerate the register classes.
const std::vector<CodeGenRegisterClass> &RegisterClasses = ArrayRef<CodeGenRegisterClass*> RegisterClasses =
Target.getRegisterClasses(); Target.getRegBank().getRegClasses();
O << "namespace { // Register classes\n"; O << "namespace { // Register classes\n";
O << " enum RegClass {\n"; O << " enum RegClass {\n";
@ -712,7 +712,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
// Emit the register enum value for each RegisterClass. // Emit the register enum value for each RegisterClass.
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
if (I != 0) O << ",\n"; if (I != 0) O << ",\n";
O << " RC_" << RegisterClasses[I].TheDef->getName(); O << " RC_" << RegisterClasses[I]->TheDef->getName();
} }
O << "\n };\n"; O << "\n };\n";
@ -729,7 +729,7 @@ void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
O << " default: break;\n"; O << " default: break;\n";
for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) { for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
const CodeGenRegisterClass &RC = RegisterClasses[I]; const CodeGenRegisterClass &RC = *RegisterClasses[I];
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName(); std::string Name = RC.TheDef->getName();

15
utils/TableGen/CodeGenRegisters.cpp
View File

@ -391,8 +391,11 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
throw std::string("No 'RegisterClass' subclasses defined!"); throw std::string("No 'RegisterClass' subclasses defined!");
RegClasses.reserve(RCs.size()); RegClasses.reserve(RCs.size());
for (unsigned i = 0, e = RCs.size(); i != e; ++i) for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
RegClasses.push_back(CodeGenRegisterClass(*this, RCs[i])); CodeGenRegisterClass *RC = new CodeGenRegisterClass(*this, RCs[i]);
RegClasses.push_back(RC);
Def2RC[RCs[i]] = RC;
}
} }
CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
@ -405,10 +408,6 @@ CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
} }
CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
if (Def2RC.empty())
for (unsigned i = 0, e = RegClasses.size(); i != e; ++i)
Def2RC[RegClasses[i].TheDef] = &RegClasses[i];
if (CodeGenRegisterClass *RC = Def2RC[Def]) if (CodeGenRegisterClass *RC = Def2RC[Def])
return RC; return RC;
@ -579,10 +578,10 @@ void CodeGenRegBank::computeDerivedInfo() {
const CodeGenRegisterClass* const CodeGenRegisterClass*
CodeGenRegBank::getRegClassForRegister(Record *R) { CodeGenRegBank::getRegClassForRegister(Record *R) {
const CodeGenRegister *Reg = getReg(R); const CodeGenRegister *Reg = getReg(R);
const std::vector<CodeGenRegisterClass> &RCs = getRegClasses(); ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses();
const CodeGenRegisterClass *FoundRC = 0; const CodeGenRegisterClass *FoundRC = 0;
for (unsigned i = 0, e = RCs.size(); i != e; ++i) { for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RCs[i]; const CodeGenRegisterClass &RC = *RCs[i];
if (!RC.contains(Reg)) if (!RC.contains(Reg))
continue; continue;

4
utils/TableGen/CodeGenRegisters.h
View File

@ -151,7 +151,7 @@ namespace llvm {
std::vector<CodeGenRegister*> Registers; std::vector<CodeGenRegister*> Registers;
DenseMap<Record*, CodeGenRegister*> Def2Reg; DenseMap<Record*, CodeGenRegister*> Def2Reg;
std::vector<CodeGenRegisterClass> RegClasses; std::vector<CodeGenRegisterClass*> RegClasses;
DenseMap<Record*, CodeGenRegisterClass*> Def2RC; DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
// Composite SubRegIndex instances. // Composite SubRegIndex instances.
@ -184,7 +184,7 @@ namespace llvm {
// Find a register from its Record def. // Find a register from its Record def.
CodeGenRegister *getReg(Record*); CodeGenRegister *getReg(Record*);
const std::vector<CodeGenRegisterClass> &getRegClasses() { ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
return RegClasses; return RegClasses;
} }

10
utils/TableGen/CodeGenTarget.cpp
View File

@ -184,9 +184,9 @@ std::vector<MVT::SimpleValueType> CodeGenTarget::
getRegisterVTs(Record *R) const { getRegisterVTs(Record *R) const {
const CodeGenRegister *Reg = getRegBank().getReg(R); const CodeGenRegister *Reg = getRegBank().getReg(R);
std::vector<MVT::SimpleValueType> Result; std::vector<MVT::SimpleValueType> Result;
const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses();
for (unsigned i = 0, e = RCs.size(); i != e; ++i) { for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RCs[i]; const CodeGenRegisterClass &RC = *RCs[i];
if (RC.contains(Reg)) { if (RC.contains(Reg)) {
const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
Result.insert(Result.end(), InVTs.begin(), InVTs.end()); Result.insert(Result.end(), InVTs.begin(), InVTs.end());
@ -201,10 +201,10 @@ getRegisterVTs(Record *R) const {
void CodeGenTarget::ReadLegalValueTypes() const { void CodeGenTarget::ReadLegalValueTypes() const {
const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses();
for (unsigned i = 0, e = RCs.size(); i != e; ++i) for (unsigned i = 0, e = RCs.size(); i != e; ++i)
for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) for (unsigned ri = 0, re = RCs[i]->VTs.size(); ri != re; ++ri)
LegalValueTypes.push_back(RCs[i].VTs[ri]); LegalValueTypes.push_back(RCs[i]->VTs[ri]);
// Remove duplicates. // Remove duplicates.
std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); std::sort(LegalValueTypes.begin(), LegalValueTypes.end());

4
utils/TableGen/CodeGenTarget.h
View File

@ -107,10 +107,6 @@ public:
return RegAltNameIndices; return RegAltNameIndices;
} }
const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
return getRegBank().getRegClasses();
}
const CodeGenRegisterClass &getRegisterClass(Record *R) const { const CodeGenRegisterClass &getRegisterClass(Record *R) const {
return *getRegBank().getRegClass(R); return *getRegBank().getRegClass(R);
} }

4
utils/TableGen/DAGISelMatcherGen.cpp
View File

@ -26,10 +26,10 @@ static MVT::SimpleValueType getRegisterValueType(Record *R,
bool FoundRC = false; bool FoundRC = false;
MVT::SimpleValueType VT = MVT::Other; MVT::SimpleValueType VT = MVT::Other;
const CodeGenRegister *Reg = T.getRegBank().getReg(R); const CodeGenRegister *Reg = T.getRegBank().getReg(R);
const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses(); ArrayRef<CodeGenRegisterClass*> RCs = T.getRegBank().getRegClasses();
for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RCs[rc]; const CodeGenRegisterClass &RC = *RCs[rc];
if (!RC.contains(Reg)) if (!RC.contains(Reg))
continue; continue;

52
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -57,8 +57,7 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS,
if (!Namespace.empty()) if (!Namespace.empty())
OS << "}\n"; OS << "}\n";
const std::vector<CodeGenRegisterClass> &RegisterClasses = ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
Target.getRegisterClasses();
if (!RegisterClasses.empty()) { if (!RegisterClasses.empty()) {
OS << "\n// Register classes\n"; OS << "\n// Register classes\n";
if (!Namespace.empty()) if (!Namespace.empty())
@ -66,7 +65,7 @@ RegisterInfoEmitter::runEnums(raw_ostream &OS,
OS << "enum {\n"; OS << "enum {\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n"; if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID"; OS << " " << RegisterClasses[i]->getName() << "RegClassID";
OS << " = " << i; OS << " = " << i;
} }
OS << "\n };\n"; OS << "\n };\n";
@ -322,15 +321,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
} }
OS << "};\n\n"; // End of register descriptors... OS << "};\n\n"; // End of register descriptors...
const std::vector<CodeGenRegisterClass> &RegisterClasses = ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
Target.getRegisterClasses();
// Loop over all of the register classes... emitting each one. // Loop over all of the register classes... emitting each one.
OS << "namespace { // Register classes...\n"; OS << "namespace { // Register classes...\n";
// Emit the register enum value arrays for each RegisterClass // Emit the register enum value arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
ArrayRef<Record*> Order = RC.getOrder(); ArrayRef<Record*> Order = RC.getOrder();
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
@ -363,7 +361,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n"; OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
OS << " MCRegisterClass("; OS << " MCRegisterClass(";
if (!RC.Namespace.empty()) if (!RC.Namespace.empty())
OS << RC.Namespace << "::"; OS << RC.Namespace << "::";
@ -439,15 +437,14 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
OS << "}\n"; OS << "}\n";
} }
const std::vector<CodeGenRegisterClass> &RegisterClasses = ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
Target.getRegisterClasses();
if (!RegisterClasses.empty()) { if (!RegisterClasses.empty()) {
OS << "namespace " << RegisterClasses[0].Namespace OS << "namespace " << RegisterClasses[0]->Namespace
<< " { // Register classes\n"; << " { // Register classes\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i]; const CodeGenRegisterClass &RC = *RegisterClasses[i];
const std::string &Name = RC.getName(); const std::string &Name = RC.getName();
// Output the register class definition. // Output the register class definition.
@ -488,15 +485,14 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< "MCRegisterClasses[];\n"; << "MCRegisterClasses[];\n";
// Start out by emitting each of the register classes. // Start out by emitting each of the register classes.
const std::vector<CodeGenRegisterClass> &RegisterClasses = ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
Target.getRegisterClasses();
// Collect all registers belonging to any allocatable class. // Collect all registers belonging to any allocatable class.
std::set<Record*> AllocatableRegs; std::set<Record*> AllocatableRegs;
// Collect allocatable registers. // Collect allocatable registers.
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
ArrayRef<Record*> Order = RC.getOrder(); ArrayRef<Record*> Order = RC.getOrder();
if (RC.Allocatable) if (RC.Allocatable)
@ -507,7 +503,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the ValueType arrays for each RegisterClass // Emit the ValueType arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.getName() + "VTs"; std::string Name = RC.getName() + "VTs";
@ -525,11 +521,11 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Now that all of the structs have been emitted, emit the instances. // Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) { if (!RegisterClasses.empty()) {
OS << "namespace " << RegisterClasses[0].Namespace OS << "namespace " << RegisterClasses[0]->Namespace
<< " { // Register class instances\n"; << " { // Register class instances\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
OS << " " << RegisterClasses[i].getName() << "Class\t" OS << " " << RegisterClasses[i]->getName() << "Class\t"
<< RegisterClasses[i].getName() << "RegClass;\n"; << RegisterClasses[i]->getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap; std::map<unsigned, std::set<unsigned> > SuperClassMap;
std::map<unsigned, std::set<unsigned> > SuperRegClassMap; std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
@ -540,7 +536,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
if (NumSubRegIndices) { if (NumSubRegIndices) {
// Emit the sub-register classes for each RegisterClass // Emit the sub-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
std::vector<Record*> SRC(NumSubRegIndices); std::vector<Record*> SRC(NumSubRegIndices);
for (DenseMap<Record*,Record*>::const_iterator for (DenseMap<Record*,Record*>::const_iterator
i = RC.SubRegClasses.begin(), i = RC.SubRegClasses.begin(),
@ -551,7 +547,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Find the register class number of i->second for SuperRegClassMap. // Find the register class number of i->second for SuperRegClassMap.
for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
if (RC2.TheDef == i->second) { if (RC2.TheDef == i->second) {
SuperRegClassMap[rc2].insert(rc); SuperRegClassMap[rc2].insert(rc);
break; break;
@ -580,7 +576,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the super-register classes for each RegisterClass // Emit the super-register classes for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName(); std::string Name = RC.TheDef->getName();
@ -596,7 +592,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
if (I != SuperRegClassMap.end()) { if (I != SuperRegClassMap.end()) {
for (std::set<unsigned>::iterator II = I->second.begin(), for (std::set<unsigned>::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II) { EE = I->second.end(); II != EE; ++II) {
const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
if (!Empty) if (!Empty)
OS << ", "; OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
@ -615,7 +611,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit the sub-classes array for each RegisterClass // Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName(); std::string Name = RC.TheDef->getName();
@ -627,7 +623,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
bool Empty = true; bool Empty = true;
for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
// Sub-classes are used to determine if a virtual register can be used // Sub-classes are used to determine if a virtual register can be used
// as an instruction operand, or if it must be copied first. // as an instruction operand, or if it must be copied first.
@ -651,7 +647,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
} }
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc]; const CodeGenRegisterClass &RC = *RegisterClasses[rc];
// Give the register class a legal C name if it's anonymous. // Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName(); std::string Name = RC.TheDef->getName();
@ -667,7 +663,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
if (I != SuperClassMap.end()) { if (I != SuperClassMap.end()) {
for (std::set<unsigned>::iterator II = I->second.begin(), for (std::set<unsigned>::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II) { EE = I->second.end(); II != EE; ++II) {
const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
if (!Empty) OS << ", "; if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false; Empty = false;
@ -680,7 +676,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit methods. // Emit methods.
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i]; const CodeGenRegisterClass &RC = *RegisterClasses[i];
OS << RC.getName() << "Class::" << RC.getName() OS << RC.getName() << "Class::" << RC.getName()
<< "Class() : TargetRegisterClass(&" << "Class() : TargetRegisterClass(&"
<< Target.getName() << "MCRegisterClasses[" << Target.getName() << "MCRegisterClasses["
@ -727,7 +723,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "\nnamespace {\n"; OS << "\nnamespace {\n";
OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) OS << " &" << getQualifiedName(RegisterClasses[i]->TheDef)
<< "RegClass,\n"; << "RegClass,\n";
OS << " };\n"; OS << " };\n";
OS << "}\n"; // End of anonymous namespace... OS << "}\n"; // End of anonymous namespace...