diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 35502aa4cd9..696547d556d 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -594,7 +594,7 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
     // We allow inline assembler nodes with empty bodies - they can
     // implicitly define registers, which is ok for JIT.
     if (MI.getOperand(0).getSymbolName()[0]) {
-      llvm_report_error("JIT does not support inline asm!\n");
+      llvm_report_error("JIT does not support inline asm!");
     }
     break;
   }
diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp
index c9e04c9506f..a030a8c4222 100644
--- a/lib/Target/ARM/ARMJITInfo.cpp
+++ b/lib/Target/ARM/ARMJITInfo.cpp
@@ -104,7 +104,7 @@ extern "C" {
       );
 #else  // Not an ARM host
   void ARMCompilationCallback() {
-    LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
+    LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!");
   }
 #endif
 }
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 094f8c2f999..8e675eba9a6 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -194,7 +194,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
 
         switch (getValueType(I->getType()).getSimpleVT()) {
           default:
-            LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg.\n"); 
+            LLVM_UNREACHABLE("ERROR in LowerArgs: can't lower this type of arg."); 
           case MVT::f32:
             // fixme? (well, will need to for weird FP structy stuff,
             // see intel ABI docs)
@@ -493,7 +493,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
   if (InFlag.getNode())
     CallOperands.push_back(InFlag);
   else
-    LLVM_UNREACHABLE("this should never happen!\n");
+    LLVM_UNREACHABLE("this should never happen!");
 
   // to make way for a hack:
   Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index 0537c3ed01a..c76ca325f78 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -129,8 +129,7 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
   } else if (RC == IA64::PRRegisterClass) {
     Opc = IA64::ST1;
   } else {
-    LLVM_UNREACHABLE(
-      "sorry, I don't know how to store this sort of reg\n");
+    LLVM_UNREACHABLE("sorry, I don't know how to store this sort of reg");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -165,7 +164,7 @@ void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
       .addReg(IA64::r0);
   } else {
     LLVM_UNREACHABLE(
-           "sorry, I don't know how to load this sort of reg from the stack\n");
+      "sorry, I don't know how to load this sort of reg from the stack");
   }
 }
 
@@ -182,7 +181,7 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
     Opc = IA64::LD1;
   } else {
     LLVM_UNREACHABLE(
-      "sorry, I don't know how to load this sort of reg\n");
+      "sorry, I don't know how to load this sort of reg");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index b9f1dbd984b..4d0ee8d8c99 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -55,7 +55,7 @@ void X86ATTAsmPrinter::PrintPICBaseSymbol() const {
   else if (Subtarget->isTargetELF())
     O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
   else
-    LLVM_UNREACHABLE( "Don't know how to print PIC label!\n");
+    LLVM_UNREACHABLE( "Don't know how to print PIC label!");
 }
 
 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp
index 5b44e4f6de4..4cc27efa1c0 100644
--- a/lib/Target/X86/X86JITInfo.cpp
+++ b/lib/Target/X86/X86JITInfo.cpp
@@ -322,7 +322,7 @@ extern "C" {
 
 #else // Not an i386 host
   void X86CompilationCallback() {
-    LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n");
+    LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
   }
 #endif
 }
@@ -554,7 +554,7 @@ char* X86JITInfo::allocateThreadLocalMemory(size_t size) {
   TLSOffset -= size;
   return TLSOffset;
 #else
-  LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!\n");
+  LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
   return 0;
 #endif
 }
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index 147d29d870b..ea355047661 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
                             const TargetRegisterClass *RC,
                             SmallVectorImpl<MachineInstr*> &NewMIs) const
 {
-  LLVM_UNREACHABLE("unimplemented\n");
+  LLVM_UNREACHABLE("unimplemented");
 }
 
 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                               const TargetRegisterClass *RC,
                               SmallVectorImpl<MachineInstr*> &NewMIs) const
 {
-  LLVM_UNREACHABLE("unimplemented\n");
+  LLVM_UNREACHABLE("unimplemented");
 }
 
 bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp
index f0ff246c2c9..7773064addf 100644
--- a/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -257,7 +257,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               .addReg(ScratchReg, RegState::Kill);
         break;
       default:
-        LLVM_UNREACHABLE("Unexpected Opcode\n");
+        LLVM_UNREACHABLE("Unexpected Opcode");
       }
     } else {
       switch (MI.getOpcode()) {
@@ -278,7 +278,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               .addImm(Offset);
         break;
       default:
-        LLVM_UNREACHABLE("Unexpected Opcode\n");
+        LLVM_UNREACHABLE("Unexpected Opcode");
       }
     }
   } else {
@@ -309,7 +309,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
             .addImm(Offset);
       break;
     default:
-      LLVM_UNREACHABLE("Unexpected Opcode\n");
+      LLVM_UNREACHABLE("Unexpected Opcode");
     }
   }
   // Erase old instruction.
diff --git a/lib/VMCore/Constants.cpp b/lib/VMCore/Constants.cpp
index 0f3239baebe..38b30c281ee 100644
--- a/lib/VMCore/Constants.cpp
+++ b/lib/VMCore/Constants.cpp
@@ -1121,7 +1121,7 @@ namespace llvm {
   template<class ConstantClass, class TypeClass>
   struct VISIBILITY_HIDDEN ConvertConstantType {
     static void convert(ConstantClass *OldC, const TypeClass *NewTy) {
-      LLVM_UNREACHABLE("This type cannot be converted!\n");
+      LLVM_UNREACHABLE("This type cannot be converted!");
     }
   };