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Fold constant adds into loads and stores to frame indices.
For the following code: double %ext(int %A.0__, long %A.1__) { %A_addr = alloca %typedef.DComplex ; <%typedef.DComplex*> [#uses=2] %tmp.1 = cast %typedef.DComplex* %A_addr to int* ; <int*> [#uses=1] store int %A.0__, int* %tmp.1 %tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1 ; <double*> [#uses=2] %tmp.3 = cast double* %tmp.2 to long* ; <long*> [#uses=1] store long %A.1__, long* %tmp.3 %tmp.5 = load double* %tmp.2 ; <double> [#uses=1] ret double %tmp.5 } We now generate: _ext: .LBB_ext_0: ; stw r3, -12(r1) stw r4, -8(r1) stw r5, -4(r1) lfd f1, -8(r1) blr Instead of: _ext: .LBB_ext_0: ; stw r3, -12(r1) addi r2, r1, -12 stw r4, 4(r2) stw r5, 8(r2) lfd f1, 4(r2) blr This also fires hundreds of times on MultiSource. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22533 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -511,7 +511,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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namespace {
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Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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Statistic<>MultiBranch("ppc-codegen", "Number of setcc logical ops collapsed");
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Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// SelectionDAG operations.
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@ -569,7 +569,7 @@ public:
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unsigned SelectExpr(SDOperand N, bool Recording=false);
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void Select(SDOperand N);
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bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
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unsigned SelectAddr(SDOperand N, unsigned& Reg, int& offset);
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void SelectBranchCC(SDOperand N);
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};
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@ -1189,7 +1189,6 @@ unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
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break;
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case ISD::OR:
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case ISD::AND:
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++MultiBranch;
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Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0);
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Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1);
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CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1);
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@ -1213,21 +1212,30 @@ unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
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}
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/// Check to see if the load is a constant offset from a base register
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bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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unsigned ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
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{
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unsigned imm = 0, opcode = N.getOpcode();
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if (N.getOpcode() == ISD::ADD) {
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Reg = SelectExpr(N.getOperand(0));
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bool isFrame = N.getOperand(0).getOpcode() == ISD::FrameIndex;
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if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
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offset = imm;
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return false;
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if (isFrame) {
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++FrameOff;
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Reg = cast<FrameIndexSDNode>(N.getOperand(0))->getIndex();
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return 1;
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} else {
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Reg = SelectExpr(N.getOperand(0));
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return 0;
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}
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} else {
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Reg = SelectExpr(N.getOperand(0));
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offset = SelectExpr(N.getOperand(1));
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return true;
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return 2;
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}
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}
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Reg = SelectExpr(N);
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offset = 0;
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return false;
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return 0;
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}
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void ISel::SelectBranchCC(SDOperand N)
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@ -1443,12 +1451,18 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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}
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} else {
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int offset;
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bool idx = SelectAddr(Address, Tmp1, offset);
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if (idx) {
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switch(SelectAddr(Address, Tmp1, offset)) {
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default: assert(0 && "Unhandled return value from SelectAddr");
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case 0: // imm offset, no frame, no index
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BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
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break;
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case 1: // imm offset + frame index
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addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1, offset);
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break;
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case 2: // base+index addressing
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Opc = IndexedOpForOp(Opc);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(offset);
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} else {
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BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
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break;
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}
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}
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return Result;
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@ -2495,12 +2509,18 @@ void ISel::Select(SDOperand N) {
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}
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} else {
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int offset;
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bool idx = SelectAddr(Address, Tmp2, offset);
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if (idx) {
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switch(SelectAddr(Address, Tmp2, offset)) {
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default: assert(0 && "Unhandled return value from SelectAddr");
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case 0: // imm offset, no frame, no index
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BuildMI(BB, Opc, 3).addReg(Tmp1).addSImm(offset).addReg(Tmp2);
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break;
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case 1: // imm offset + frame index
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addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2, offset);
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break;
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case 2: // base+index addressing
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Opc = IndexedOpForOp(Opc);
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BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
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} else {
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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break;
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}
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}
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return;
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