mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 17:55:18 +00:00
Print % signs before register names; turn off "noprefix" mode in gas output.
Fixes test case test/Programs/LLVMSource/2003-08-03-ReservedWordGlobal.ll. Also: Refactor implicit-uses printing into its own method. Remove a couple of unused variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7737 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke
parent
a8f5de3942
commit
2a09877519
@ -55,6 +55,7 @@ namespace {
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return "X86 Assembly Printer";
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}
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void checkImplUses (const TargetInstrDescriptor &Desc);
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO,
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bool elideOffsetKeyword = false);
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@ -441,6 +442,8 @@ static bool isMem(const MachineInstr *MI, unsigned Op) {
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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void Printer::printOp(const MachineOperand &MO,
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bool elideOffsetKeyword /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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@ -453,7 +456,8 @@ void Printer::printOp(const MachineOperand &MO,
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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@ -497,7 +501,6 @@ static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
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}
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void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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@ -548,6 +551,19 @@ void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
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O << "]";
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}
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/// checkImplUses - Emit the implicit-use registers for the
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/// instruction described by DESC, if its PrintImplUses flag is set.
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///
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void Printer::checkImplUses (const TargetInstrDescriptor &Desc) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << ", %" << RI.get(*p).Name;
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}
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}
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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@ -555,7 +571,6 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::Pseudo:
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@ -647,11 +662,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << ", ";
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printOp(MI->getOperand(1));
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}
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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O << ", " << RI.get(*p).Name;
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}
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}
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checkImplUses(Desc);
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O << "\n";
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return;
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}
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@ -782,11 +793,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << ", ";
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printOp(MI->getOperand(MI->getNumOperands()-1));
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}
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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O << ", " << RI.get(*p).Name;
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}
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}
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checkImplUses(Desc);
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O << "\n";
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return;
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@ -898,9 +905,17 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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bool Printer::doInitialization(Module &M)
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{
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// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly,
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// with no % decorations on register names.
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O << "\t.intel_syntax noprefix\n";
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// Tell gas we are outputting Intel syntax (not AT&T syntax)
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// assembly.
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//
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// Bug: gas in `intel_syntax noprefix' mode interprets the symbol
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// `Sp' in an instruction as a reference to the register named sp,
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// and if you try to reference a symbol `Sp' (e.g. `mov ECX, OFFSET
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// Sp') then it gets lowercased before being looked up in the symbol
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// table. This creates spurious `undefined symbol' errors when
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// linking. Workaround: Do not use `noprefix' mode, and decorate all
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// register names with percent signs.
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O << "\t.intel_syntax\n";
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Mang = new Mangler(M);
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return false; // success
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}
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@ -55,6 +55,7 @@ namespace {
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return "X86 Assembly Printer";
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}
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void checkImplUses (const TargetInstrDescriptor &Desc);
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO,
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bool elideOffsetKeyword = false);
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@ -441,6 +442,8 @@ static bool isMem(const MachineInstr *MI, unsigned Op) {
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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}
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void Printer::printOp(const MachineOperand &MO,
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bool elideOffsetKeyword /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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@ -453,7 +456,8 @@ void Printer::printOp(const MachineOperand &MO,
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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@ -497,7 +501,6 @@ static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
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}
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void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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@ -548,6 +551,19 @@ void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
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O << "]";
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}
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/// checkImplUses - Emit the implicit-use registers for the
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/// instruction described by DESC, if its PrintImplUses flag is set.
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///
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void Printer::checkImplUses (const TargetInstrDescriptor &Desc) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << ", %" << RI.get(*p).Name;
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}
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}
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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@ -555,7 +571,6 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::Pseudo:
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@ -647,11 +662,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << ", ";
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printOp(MI->getOperand(1));
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}
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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O << ", " << RI.get(*p).Name;
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}
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}
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checkImplUses(Desc);
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O << "\n";
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return;
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}
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@ -782,11 +793,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << ", ";
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printOp(MI->getOperand(MI->getNumOperands()-1));
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}
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if (Desc.TSFlags & X86II::PrintImplUses) {
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for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
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O << ", " << RI.get(*p).Name;
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}
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}
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checkImplUses(Desc);
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O << "\n";
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return;
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@ -898,9 +905,17 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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bool Printer::doInitialization(Module &M)
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{
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// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly,
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// with no % decorations on register names.
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O << "\t.intel_syntax noprefix\n";
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// Tell gas we are outputting Intel syntax (not AT&T syntax)
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// assembly.
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//
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// Bug: gas in `intel_syntax noprefix' mode interprets the symbol
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// `Sp' in an instruction as a reference to the register named sp,
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// and if you try to reference a symbol `Sp' (e.g. `mov ECX, OFFSET
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// Sp') then it gets lowercased before being looked up in the symbol
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// table. This creates spurious `undefined symbol' errors when
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// linking. Workaround: Do not use `noprefix' mode, and decorate all
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// register names with percent signs.
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O << "\t.intel_syntax\n";
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Mang = new Mangler(M);
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return false; // success
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}
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