mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Make sure the correct opcodes are used to SUB and ADD the stack
pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
43213cf1ac
commit
2a1b60d791
@ -55,8 +55,8 @@ bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
|
|||||||
MMI.callsUnwindInit() || MMI.callsEHReturn());
|
MMI.callsUnwindInit() || MMI.callsEHReturn());
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
|
static unsigned getSUBriOpcode(unsigned isLP64, int64_t Imm) {
|
||||||
if (is64Bit) {
|
if (isLP64) {
|
||||||
if (isInt<8>(Imm))
|
if (isInt<8>(Imm))
|
||||||
return X86::SUB64ri8;
|
return X86::SUB64ri8;
|
||||||
return X86::SUB64ri32;
|
return X86::SUB64ri32;
|
||||||
@ -67,8 +67,8 @@ static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
|
static unsigned getADDriOpcode(unsigned isLP64, int64_t Imm) {
|
||||||
if (is64Bit) {
|
if (isLP64) {
|
||||||
if (isInt<8>(Imm))
|
if (isInt<8>(Imm))
|
||||||
return X86::ADD64ri8;
|
return X86::ADD64ri8;
|
||||||
return X86::ADD64ri32;
|
return X86::ADD64ri32;
|
||||||
@ -145,7 +145,7 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
|
|||||||
static
|
static
|
||||||
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned StackPtr, int64_t NumBytes,
|
unsigned StackPtr, int64_t NumBytes,
|
||||||
bool Is64Bit, bool UseLEA,
|
bool Is64Bit, bool IsLP64, bool UseLEA,
|
||||||
const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
|
const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
|
||||||
bool isSub = NumBytes < 0;
|
bool isSub = NumBytes < 0;
|
||||||
uint64_t Offset = isSub ? -NumBytes : NumBytes;
|
uint64_t Offset = isSub ? -NumBytes : NumBytes;
|
||||||
@ -154,8 +154,8 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|||||||
Opc = getLEArOpcode(Is64Bit);
|
Opc = getLEArOpcode(Is64Bit);
|
||||||
else
|
else
|
||||||
Opc = isSub
|
Opc = isSub
|
||||||
? getSUBriOpcode(Is64Bit, Offset)
|
? getSUBriOpcode(IsLP64, Offset)
|
||||||
: getADDriOpcode(Is64Bit, Offset);
|
: getADDriOpcode(IsLP64, Offset);
|
||||||
|
|
||||||
uint64_t Chunk = (1LL << 31) - 1;
|
uint64_t Chunk = (1LL << 31) - 1;
|
||||||
DebugLoc DL = MBB.findDebugLoc(MBBI);
|
DebugLoc DL = MBB.findDebugLoc(MBBI);
|
||||||
@ -660,6 +660,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
|
uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
|
||||||
bool HasFP = hasFP(MF);
|
bool HasFP = hasFP(MF);
|
||||||
bool Is64Bit = STI.is64Bit();
|
bool Is64Bit = STI.is64Bit();
|
||||||
|
bool IsLP64 = STI.isTarget64BitLP64();
|
||||||
bool IsWin64 = STI.isTargetWin64();
|
bool IsWin64 = STI.isTargetWin64();
|
||||||
bool UseLEA = STI.useLeaForSP();
|
bool UseLEA = STI.useLeaForSP();
|
||||||
unsigned StackAlign = getStackAlignment();
|
unsigned StackAlign = getStackAlignment();
|
||||||
@ -711,7 +712,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
if (TailCallReturnAddrDelta < 0) {
|
if (TailCallReturnAddrDelta < 0) {
|
||||||
MachineInstr *MI =
|
MachineInstr *MI =
|
||||||
BuildMI(MBB, MBBI, DL,
|
BuildMI(MBB, MBBI, DL,
|
||||||
TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
|
TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
|
||||||
StackPtr)
|
StackPtr)
|
||||||
.addReg(StackPtr)
|
.addReg(StackPtr)
|
||||||
.addImm(-TailCallReturnAddrDelta)
|
.addImm(-TailCallReturnAddrDelta)
|
||||||
@ -927,7 +928,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
// MSVC x64's __chkstk needs to adjust %rsp.
|
// MSVC x64's __chkstk needs to adjust %rsp.
|
||||||
// FIXME: %rax preserves the offset and should be available.
|
// FIXME: %rax preserves the offset and should be available.
|
||||||
if (isSPUpdateNeeded)
|
if (isSPUpdateNeeded)
|
||||||
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
|
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
|
||||||
UseLEA, TII, *RegInfo);
|
UseLEA, TII, *RegInfo);
|
||||||
|
|
||||||
if (isEAXAlive) {
|
if (isEAXAlive) {
|
||||||
@ -939,7 +940,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
MBB.insert(MBBI, MI);
|
MBB.insert(MBBI, MI);
|
||||||
}
|
}
|
||||||
} else if (NumBytes)
|
} else if (NumBytes)
|
||||||
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
|
emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
|
||||||
UseLEA, TII, *RegInfo);
|
UseLEA, TII, *RegInfo);
|
||||||
|
|
||||||
// If we need a base pointer, set it up here. It's whatever the value
|
// If we need a base pointer, set it up here. It's whatever the value
|
||||||
@ -996,6 +997,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
unsigned RetOpcode = MBBI->getOpcode();
|
unsigned RetOpcode = MBBI->getOpcode();
|
||||||
DebugLoc DL = MBBI->getDebugLoc();
|
DebugLoc DL = MBBI->getDebugLoc();
|
||||||
bool Is64Bit = STI.is64Bit();
|
bool Is64Bit = STI.is64Bit();
|
||||||
|
bool IsLP64 = STI.isTarget64BitLP64();
|
||||||
bool UseLEA = STI.useLeaForSP();
|
bool UseLEA = STI.useLeaForSP();
|
||||||
unsigned StackAlign = getStackAlignment();
|
unsigned StackAlign = getStackAlignment();
|
||||||
unsigned SlotSize = RegInfo->getSlotSize();
|
unsigned SlotSize = RegInfo->getSlotSize();
|
||||||
@ -1091,7 +1093,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
}
|
}
|
||||||
} else if (NumBytes) {
|
} else if (NumBytes) {
|
||||||
// Adjust stack pointer back: ESP += numbytes.
|
// Adjust stack pointer back: ESP += numbytes.
|
||||||
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo);
|
emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
|
||||||
|
TII, *RegInfo);
|
||||||
}
|
}
|
||||||
|
|
||||||
// We're returning from function via eh_return.
|
// We're returning from function via eh_return.
|
||||||
@ -1126,7 +1129,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
if (Offset) {
|
if (Offset) {
|
||||||
// Check for possible merge with preceding ADD instruction.
|
// Check for possible merge with preceding ADD instruction.
|
||||||
Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
||||||
emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo);
|
emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
|
||||||
|
UseLEA, TII, *RegInfo);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Jump to label or value in register.
|
// Jump to label or value in register.
|
||||||
@ -1169,7 +1173,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
|
|
||||||
// Check for possible merge with preceding ADD instruction.
|
// Check for possible merge with preceding ADD instruction.
|
||||||
delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
|
||||||
emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo);
|
emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
|
||||||
|
*RegInfo);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user