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https://github.com/c64scene-ar/llvm-6502.git
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Make sure the correct opcodes are used to SUB and ADD the stack
pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174446 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -55,8 +55,8 @@ bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
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MMI.callsUnwindInit() || MMI.callsEHReturn());
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}
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static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
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if (is64Bit) {
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static unsigned getSUBriOpcode(unsigned isLP64, int64_t Imm) {
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if (isLP64) {
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if (isInt<8>(Imm))
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return X86::SUB64ri8;
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return X86::SUB64ri32;
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@ -67,8 +67,8 @@ static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
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}
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}
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static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
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if (is64Bit) {
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static unsigned getADDriOpcode(unsigned isLP64, int64_t Imm) {
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if (isLP64) {
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if (isInt<8>(Imm))
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return X86::ADD64ri8;
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return X86::ADD64ri32;
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@ -145,7 +145,7 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
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static
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void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr, int64_t NumBytes,
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bool Is64Bit, bool UseLEA,
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bool Is64Bit, bool IsLP64, bool UseLEA,
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const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
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bool isSub = NumBytes < 0;
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uint64_t Offset = isSub ? -NumBytes : NumBytes;
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@ -154,8 +154,8 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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Opc = getLEArOpcode(Is64Bit);
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else
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Opc = isSub
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? getSUBriOpcode(Is64Bit, Offset)
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: getADDriOpcode(Is64Bit, Offset);
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? getSUBriOpcode(IsLP64, Offset)
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: getADDriOpcode(IsLP64, Offset);
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uint64_t Chunk = (1LL << 31) - 1;
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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@ -660,6 +660,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
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bool HasFP = hasFP(MF);
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bool Is64Bit = STI.is64Bit();
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bool IsLP64 = STI.isTarget64BitLP64();
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bool IsWin64 = STI.isTargetWin64();
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bool UseLEA = STI.useLeaForSP();
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unsigned StackAlign = getStackAlignment();
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@ -711,7 +712,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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if (TailCallReturnAddrDelta < 0) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
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TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
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StackPtr)
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.addReg(StackPtr)
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.addImm(-TailCallReturnAddrDelta)
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@ -927,7 +928,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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// MSVC x64's __chkstk needs to adjust %rsp.
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// FIXME: %rax preserves the offset and should be available.
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if (isSPUpdateNeeded)
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emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
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emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
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UseLEA, TII, *RegInfo);
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if (isEAXAlive) {
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@ -939,7 +940,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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MBB.insert(MBBI, MI);
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}
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} else if (NumBytes)
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emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
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emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
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UseLEA, TII, *RegInfo);
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// If we need a base pointer, set it up here. It's whatever the value
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@ -996,6 +997,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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bool Is64Bit = STI.is64Bit();
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bool IsLP64 = STI.isTarget64BitLP64();
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bool UseLEA = STI.useLeaForSP();
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unsigned StackAlign = getStackAlignment();
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unsigned SlotSize = RegInfo->getSlotSize();
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@ -1091,7 +1093,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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}
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} else if (NumBytes) {
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// Adjust stack pointer back: ESP += numbytes.
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emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo);
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emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
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TII, *RegInfo);
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}
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// We're returning from function via eh_return.
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@ -1126,7 +1129,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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if (Offset) {
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// Check for possible merge with preceding ADD instruction.
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Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
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emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo);
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emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
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UseLEA, TII, *RegInfo);
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}
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// Jump to label or value in register.
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@ -1169,7 +1173,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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// Check for possible merge with preceding ADD instruction.
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delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
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emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo);
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emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
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*RegInfo);
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}
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}
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