From 2a3868849438a0a0ad4f9a50f2b94eb1639b554e Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 29 Jul 2009 21:36:49 +0000 Subject: [PATCH] inline the global 'getInstrOperandRegClass' function into its callers now that TargetOperandInfo does the heavy lifting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetInstrInfo.h | 6 ------ lib/CodeGen/PostRASchedulerList.cpp | 11 +++++++---- .../SelectionDAG/ScheduleDAGSDNodesEmit.cpp | 15 ++++++++------- lib/CodeGen/SimpleRegisterCoalescing.cpp | 2 +- lib/CodeGen/StackSlotColoring.cpp | 4 ++-- lib/Target/TargetInstrInfo.cpp | 10 ---------- 6 files changed, 18 insertions(+), 30 deletions(-) diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 5e1a9cf9d4a..c47b418f9a3 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -488,12 +488,6 @@ public: virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; }; -/// getInstrOperandRegClass - Return register class of the operand of an -/// instruction of the specified TargetInstrDesc. -const TargetRegisterClass* -getInstrOperandRegClass(const TargetRegisterInfo *TRI, - const TargetInstrDesc &II, unsigned Op); - } // End llvm namespace #endif diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index c02647a1309..b90a6dde9cc 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -449,8 +449,10 @@ void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) { if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); + const TargetRegisterClass *NewRC = 0; + + if (i < MI->getDesc().getNumOperands()) + NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. @@ -521,8 +523,9 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, if (Reg == 0) continue; if (!MO.isUse()) continue; - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); + const TargetRegisterClass *NewRC = 0; + if (i < MI->getDesc().getNumOperands()) + NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 0cc8bbad575..e352f88afc4 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -75,8 +75,9 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, Match = false; if (User->isMachineOpcode()) { const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); - const TargetRegisterClass *RC = - getInstrOperandRegClass(TRI, II, i+II.getNumDefs()); + const TargetRegisterClass *RC = 0; + if (i+II.getNumDefs() < II.getNumOperands()) + RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); if (!UseRC) UseRC = RC; else if (RC) { @@ -160,7 +161,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, // is a vreg in the same register class, use the CopyToReg'd destination // register instead of creating a new vreg. unsigned VRBase = 0; - const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i); + const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); if (II.OpInfo[i].isOptionalDef()) { // Optional def must be a physical register. unsigned NumResults = CountResults(Node); @@ -251,10 +252,10 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op, // If the instruction requires a register in a different class, create // a new virtual register and copy the value into it. if (II) { - const TargetRegisterClass *SrcRC = - MRI.getRegClass(VReg); - const TargetRegisterClass *DstRC = - getInstrOperandRegClass(TRI, *II, IIOpNum); + const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg); + const TargetRegisterClass *DstRC = 0; + if (IIOpNum < II->getNumOperands()) + DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && "Don't have operand info for this instruction!"); if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 7aa9cf543f9..2478612d006 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -619,7 +619,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, // Make sure the copy destination register class fits the instruction // definition register class. The mismatch can happen as a result of earlier // extract_subreg, insert_subreg, subreg_to_reg coalescing. - const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0); + const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { if (mri_->getRegClass(DstReg) != RC) return false; diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index 0d9ebbbeb80..17c8929b70a 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -512,7 +512,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII, TID.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) return false; - const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i); + const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); if (RC && !RC->contains(NewReg)) return false; @@ -576,7 +576,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII, TID.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) return false; - const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i); + const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); if (RC && !RC->contains(NewReg)) return false; FoundUse = true; diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index afbadbfc63e..0f1ade2b9f9 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -47,13 +47,3 @@ TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const { return TRI->getRegClass(RegClass); } -/// getInstrOperandRegClass - Return register class of the operand of an -/// instruction of the specified TargetInstrDesc. -const TargetRegisterClass* -llvm::getInstrOperandRegClass(const TargetRegisterInfo *TRI, - const TargetInstrDesc &II, unsigned Op) { - // FIXME: Should be an assert! - if (Op >= II.getNumOperands()) - return NULL; - return II.OpInfo[Op].getRegClass(TRI); -}