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Reduce code duplication on the TLS implementation.

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This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2009-04-07 21:37:46 +00:00
parent 4fd552880c
commit 2a6411bbbd
21 changed files with 239 additions and 201 deletions
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11
lib/Target/X86/X86InstrInfo.h
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@@ -243,7 +243,7 @@ namespace X86II {
};
}
const int X86AddrNumOperands = 4;
const int X86AddrNumOperands = 5;
inline static bool isScale(const MachineOperand &MO) {
return MO.isImm() &&
@@ -251,7 +251,7 @@ inline static bool isScale(const MachineOperand &MO) {
MO.getImm() == 4 || MO.getImm() == 8);
}
inline static bool isMem(const MachineInstr *MI, unsigned Op) {
inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
if (MI->getOperand(Op).isFI()) return true;
return Op+4 <= MI->getNumOperands() &&
MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
@@ -262,6 +262,13 @@ inline static bool isMem(const MachineInstr *MI, unsigned Op) {
MI->getOperand(Op+3).isJTI());
}
inline static bool isMem(const MachineInstr *MI, unsigned Op) {
if (MI->getOperand(Op).isFI()) return true;
return Op+5 <= MI->getNumOperands() &&
MI->getOperand(Op+4).isReg() &&
isLeaMem(MI, Op);
}
class X86InstrInfo : public TargetInstrInfoImpl {
X86TargetMachine &TM;
const X86RegisterInfo RI;