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Fixed operand of SC microMIPS instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202526 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-02-28 18:22:56 +00:00
parent 0164f27742
commit 2a80d7db79
3 changed files with 23 additions and 1 deletions
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3
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -611,6 +611,9 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if (Inst.getOpcode() == Mips::SC_MM)
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));

3
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -53,10 +53,11 @@ class LLBaseMM<string opstr, RegisterOperand RO> :
}
class SCBaseMM<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rt, mem_mm_12:$addr),
InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMemMMImm12";
let mayStore = 1;
let Constraints = "$rt = $dst";
}
class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,

18
test/CodeGen/Mips/micromips-atomic.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -o - | FileCheck %s
@x = common global i32 0, align 4
define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
entry:
%0 = atomicrmw add i32* @x, i32 %incr monotonic
ret i32 %0
; CHECK-LABEL: AtomicLoadAdd32:
; CHECK: lw $[[R0:[0-9]+]], %got(x)
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
; CHECK: sc $[[R2]], 0($[[R0]])
; CHECK: beqz $[[R2]], $[[BB0]]
}