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Refactor ABI code in the PowerPC backend.

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Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2009-07-03 06:47:08 +00:00
parent ffd0200abf
commit 2a9ddfb903
12 changed files with 370 additions and 572 deletions
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6
lib/Target/PowerPC/PPCCallingConv.td
View File

@ -43,10 +43,8 @@ def CC_PPC : CallingConv<[
CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
// Common sub-targets passes FP values in F1 - F13
CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
// ELF32 sub-target pass FP values in F1 - F8.
CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
CCIfType<[f32, f64],
CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>,
// The first 12 Vector arguments are passed in altivec registers.
CCIfType<[v16i8, v8i16, v4i32, v4f32],

10
lib/Target/PowerPC/PPCCodeEmitter.cpp
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@ -163,8 +163,8 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
} else if (MO.isGlobal() || MO.isSymbol() ||
MO.isCPI() || MO.isJTI()) {
unsigned Reloc = 0;
if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho ||
MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF ||
if (MI.getOpcode() == PPC::BL_Darwin || MI.getOpcode() == PPC::BL8_Darwin ||
MI.getOpcode() == PPC::BL_SVR4 || MI.getOpcode() == PPC::BL8_ELF ||
MI.getOpcode() == PPC::TAILB || MI.getOpcode() == PPC::TAILB8)
Reloc = PPC::reloc_pcrel_bx;
else {
@ -246,9 +246,9 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
} else if (MO.isMBB()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();
if (Opcode == PPC::B || Opcode == PPC::BL_Macho ||
Opcode == PPC::BLA_Macho || Opcode == PPC::BL_ELF ||
Opcode == PPC::BLA_ELF)
if (Opcode == PPC::B || Opcode == PPC::BL_Darwin ||
Opcode == PPC::BLA_Darwin|| Opcode == PPC::BL_SVR4 ||
Opcode == PPC::BLA_SVR4)
Reloc = PPC::reloc_pcrel_bx;
else // BCC instruction
Reloc = PPC::reloc_pcrel_bcx;

36
lib/Target/PowerPC/PPCFrameInfo.h
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@ -31,68 +31,68 @@ public:
/// getReturnSaveOffset - Return the previous frame offset to save the
/// return address.
static unsigned getReturnSaveOffset(bool LP64, bool isMacho) {
if (isMacho)
static unsigned getReturnSaveOffset(bool LP64, bool isDarwinABI) {
if (isDarwinABI)
return LP64 ? 16 : 8;
// For ELF 32 ABI:
// SVR4 ABI:
return 4;
}
/// getFramePointerSaveOffset - Return the previous frame offset to save the
/// frame pointer.
static unsigned getFramePointerSaveOffset(bool LP64, bool isMacho) {
// For MachO ABI:
static unsigned getFramePointerSaveOffset(bool LP64, bool isDarwinABI) {
// For the Darwin ABI:
// Use the TOC save slot in the PowerPC linkage area for saving the frame
// pointer (if needed.) LLVM does not generate code that uses the TOC (R2
// is treated as a caller saved register.)
if (isMacho)
if (isDarwinABI)
return LP64 ? 40 : 20;
// For ELF 32 ABI:
// SVR4 ABI:
// Save it right before the link register
return -4U;
}
/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
///
static unsigned getLinkageSize(bool LP64, bool isMacho) {
if (isMacho)
static unsigned getLinkageSize(bool LP64, bool isDarwinABI) {
if (isDarwinABI)
return 6 * (LP64 ? 8 : 4);
// For ELF 32 ABI:
// SVR4 ABI:
return 8;
}
/// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
/// argument area.
static unsigned getMinCallArgumentsSize(bool LP64, bool isMacho) {
// For Macho ABI:
static unsigned getMinCallArgumentsSize(bool LP64, bool isDarwinABI) {
// For the Darwin ABI:
// The prolog code of the callee may store up to 8 GPR argument registers to
// the stack, allowing va_start to index over them in memory if its varargs.
// Because we cannot tell if this is needed on the caller side, we have to
// conservatively assume that it is needed. As such, make sure we have at
// least enough stack space for the caller to store the 8 GPRs.
if (isMacho)
if (isDarwinABI)
return 8 * (LP64 ? 8 : 4);
// For ELF 32 ABI:
// SVR4 ABI:
// There is no default stack allocated for the 8 first GPR arguments.
return 0;
}
/// getMinCallFrameSize - Return the minimum size a call frame can be using
/// the PowerPC ABI.
static unsigned getMinCallFrameSize(bool LP64, bool isMacho) {
static unsigned getMinCallFrameSize(bool LP64, bool isDarwinABI) {
// The call frame needs to be at least big enough for linkage and 8 args.
return getLinkageSize(LP64, isMacho) +
getMinCallArgumentsSize(LP64, isMacho);
return getLinkageSize(LP64, isDarwinABI) +
getMinCallArgumentsSize(LP64, isDarwinABI);
}
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
const std::pair<unsigned, int> *
getCalleeSavedSpillSlots(unsigned &NumEntries) const {
// Early exit if not using the SVR4 ABI.
if (!TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) {
if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
NumEntries = 0;
return 0;
}

2
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -159,7 +159,7 @@ getHazardType(SUnit *SU) {
}
// Do not allow MTCTR and BCTRL to be in the same dispatch group.
if (HasCTRSet && (Opcode == PPC::BCTRL_Macho || Opcode == PPC::BCTRL_ELF))
if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
return NoopHazard;
// If this is a load following a store, make sure it's not to the same or

691
lib/Target/PowerPC/PPCISelLowering.cpp
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File diff suppressed because it is too large Load Diff

19
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -82,7 +82,7 @@ namespace llvm {
STD_32,
/// CALL - A direct function call.
CALL_Macho, CALL_ELF,
CALL_Darwin, CALL_SVR4,
/// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
/// MTCTR instruction.
@ -90,7 +90,7 @@ namespace llvm {
/// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
/// BCTRL instruction.
BCTRL_Macho, BCTRL_ELF,
BCTRL_Darwin, BCTRL_SVR4,
/// Return with a flag operand, matched by 'blr'
RET_FLAG,
@ -352,7 +352,7 @@ namespace llvm {
SDValue Chain,
SDValue &LROpOut,
SDValue &FPOpOut,
bool isMachoABI,
bool isDarwinABI,
DebugLoc dl);
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
@ -376,14 +376,11 @@ namespace llvm {
unsigned &VarArgsNumGPR,
unsigned &VarArgsNumFPR,
const PPCSubtarget &Subtarget);
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
int &VarArgsFrameIndex,
int &VarArgsStackOffset,
unsigned &VarArgsNumGPR,
unsigned &VarArgsNumFPR,
const PPCSubtarget &Subtarget);
SDValue LowerCALL(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
SDValue LowerFORMAL_ARGUMENTS_Darwin(SDValue Op, SelectionDAG &DAG,
int &VarArgsFrameIndex,
const PPCSubtarget &Subtarget);
SDValue LowerCALL_Darwin(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
SDValue LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget, TargetMachine &TM);
SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM);

40
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -61,7 +61,7 @@ let Defs = [LR8] in
def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;
// Macho ABI Calls.
// Darwin ABI Calls.
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the PPC64 non-callee saved registers.
Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
@ -71,22 +71,22 @@ let isCall = 1, PPC970_Unit = 7,
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL8_Macho : IForm<18, 0, 1,
(outs), (ins calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA8_Macho : IForm<18, 1, 1,
(outs), (ins aaddr:$func, variable_ops),
"bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
def BL8_Darwin : IForm<18, 0, 1,
(outs), (ins calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA8_Darwin : IForm<18, 1, 1,
(outs), (ins aaddr:$func, variable_ops),
"bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
}
let Uses = [CTR8, RM] in {
def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_Macho)]>, Requires<[In64BitMode]>;
def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
}
}
// ELF 64 ABI Calls = Macho ABI Calls
// ELF 64 ABI Calls = Darwin ABI Calls
// Used to define BL8_ELF and BLA8_ELF
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the PPC64 non-callee saved registers.
@ -102,26 +102,26 @@ let isCall = 1, PPC970_Unit = 7,
"bl $func", BrB, []>; // See Pat patterns below.
def BLA8_ELF : IForm<18, 1, 1,
(outs), (ins aaddr:$func, variable_ops),
"bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
"bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
}
let Uses = [CTR8, RM] in {
def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_ELF)]>, Requires<[In64BitMode]>;
[(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
}
}
// Calls
def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
(BL8_Macho tglobaladdr:$dst)>;
def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
(BL8_Macho texternalsym:$dst)>;
def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
(BL8_Darwin tglobaladdr:$dst)>;
def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
(BL8_Darwin texternalsym:$dst)>;
def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
(BL8_ELF tglobaladdr:$dst)>;
def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
(BL8_ELF texternalsym:$dst)>;
// Atomic operations

66
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -107,17 +107,17 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
[SDNPHasChain, SDNPOptInFlag]>;
@ -412,7 +412,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
/*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
}
// Macho ABI Calls.
// Darwin ABI Calls.
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the non-callee saved registers...
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
@ -424,22 +424,22 @@ let isCall = 1, PPC970_Unit = 7,
CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL_Macho : IForm<18, 0, 1,
(outs), (ins calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA_Macho : IForm<18, 1, 1,
def BL_Darwin : IForm<18, 0, 1,
(outs), (ins calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA_Darwin : IForm<18, 1, 1,
(outs), (ins aaddr:$func, variable_ops),
"bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
"bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
}
let Uses = [CTR, RM] in {
def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
}
}
// ELF ABI Calls.
// SVR4 ABI Calls.
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the non-callee saved registers...
Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
@ -451,19 +451,19 @@ let isCall = 1, PPC970_Unit = 7,
CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
// Convenient aliases for call instructions
let Uses = [RM] in {
def BL_ELF : IForm<18, 0, 1,
def BL_SVR4 : IForm<18, 0, 1,
(outs), (ins calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA_ELF : IForm<18, 1, 1,
def BLA_SVR4 : IForm<18, 1, 1,
(outs), (ins aaddr:$func, variable_ops),
"bla $func", BrB,
[(PPCcall_ELF (i32 imm:$func))]>;
[(PPCcall_SVR4 (i32 imm:$func))]>;
}
let Uses = [CTR, RM] in {
def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
(outs), (ins variable_ops),
"bctrl", BrB,
[(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
}
}
@ -1389,14 +1389,14 @@ def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
(RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
// Calls
def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
(BL_Macho tglobaladdr:$dst)>;
def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
(BL_Macho texternalsym:$dst)>;
def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
(BL_ELF tglobaladdr:$dst)>;
def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
(BL_ELF texternalsym:$dst)>;
def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
(BL_Darwin tglobaladdr:$dst)>;
def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
(BL_Darwin texternalsym:$dst)>;
def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
(BL_SVR4 tglobaladdr:$dst)>;
def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
(BL_SVR4 texternalsym:$dst)>;
def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),

2
lib/Target/PowerPC/PPCJITInfo.cpp
View File

@ -354,7 +354,7 @@ void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
JCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
JCE.emitWordBE(0x7d6802a6); // mflr r11
JCE.emitWordBE(0xf9610060); // std r11, 96(r1)
} else if (TM.getSubtargetImpl()->isMachoABI()){
} else if (TM.getSubtargetImpl()->isDarwinABI()){
JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
JCE.emitWordBE(0x7d6802a6); // mflr r11
JCE.emitWordBE(0x91610028); // stw r11, 40(r1)

64
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -149,7 +149,7 @@ const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
const unsigned*
PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
// 32-bit Darwin calling convention.
static const unsigned Macho32_CalleeSavedRegs[] = {
static const unsigned Darwin32_CalleeSavedRegs[] = {
PPC::R13, PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@ -174,7 +174,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
PPC::LR, 0
};
static const unsigned ELF32_CalleeSavedRegs[] = {
static const unsigned SVR4_CalleeSavedRegs[] = {
PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@ -202,7 +202,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
PPC::LR, 0
};
// 64-bit Darwin calling convention.
static const unsigned Macho64_CalleeSavedRegs[] = {
static const unsigned Darwin64_CalleeSavedRegs[] = {
PPC::X14, PPC::X15,
PPC::X16, PPC::X17, PPC::X18, PPC::X19,
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@ -227,18 +227,17 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
PPC::LR8, 0
};
if (Subtarget.isMachoABI())
return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
Macho32_CalleeSavedRegs;
if (Subtarget.isDarwinABI())
return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
Darwin32_CalleeSavedRegs;
// ELF 32.
return ELF32_CalleeSavedRegs;
return SVR4_CalleeSavedRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
// 32-bit Macho calling convention.
static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
// 32-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
@ -267,7 +266,7 @@ PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
&PPC::GPRCRegClass, 0
};
static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
@ -298,8 +297,8 @@ PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
&PPC::GPRCRegClass, 0
};
// 64-bit Macho calling convention.
static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
// 64-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
@ -328,12 +327,11 @@ PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
&PPC::G8RCRegClass, 0
};
if (Subtarget.isMachoABI())
return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
Macho32_CalleeSavedRegClasses;
if (Subtarget.isDarwinABI())
return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
Darwin32_CalleeSavedRegClasses;
// ELF 32.
return ELF32_CalleeSavedRegClasses;
return SVR4_CalleeSavedRegClasses;
}
// needsFP - Return true if the specified function should have a dedicated frame
@ -360,7 +358,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::RM);
// The SVR4 ABI reserves r2 and r13
if (Subtarget.isELF32_ABI()) {
if (Subtarget.isSVR4ABI()) {
Reserved.set(PPC::R2); // System-reserved register
Reserved.set(PPC::R13); // Small Data Area pointer register
}
@ -929,7 +927,7 @@ void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
// Maximum call frame needs to be at least big enough for linkage and 8 args.
unsigned minCallFrameSize =
PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
Subtarget.isMachoABI());
Subtarget.isDarwinABI());
maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
// If we have dynamic alloca then maxCallFrameSize needs to be aligned so
@ -962,15 +960,15 @@ PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Save R31 if necessary
int FPSI = FI->getFramePointerSaveIndex();
bool IsPPC64 = Subtarget.isPPC64();
bool IsELF32_ABI = Subtarget.isELF32_ABI();
bool IsMachoABI = Subtarget.isMachoABI();
bool IsSVR4ABI = Subtarget.isSVR4ABI();
bool isDarwinABI = Subtarget.isDarwinABI();
MachineFrameInfo *MFI = MF.getFrameInfo();
// If the frame pointer save index hasn't been defined yet.
if (!FPSI && needsFP(MF) && IsELF32_ABI) {
if (!FPSI && needsFP(MF) && IsSVR4ABI) {
// Find out what the fix offset of the frame pointer save area.
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
IsMachoABI);
isDarwinABI);
// Allocate the frame index for frame pointer save area.
FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
// Save the result.
@ -1004,7 +1002,7 @@ void
PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
const {
// Early exit if not using the SVR4 ABI.
if (!Subtarget.isELF32_ABI()) {
if (!Subtarget.isSVR4ABI()) {
return;
}
@ -1198,24 +1196,24 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Get processor type.
bool IsPPC64 = Subtarget.isPPC64();
// Get operating system
bool IsMachoABI = Subtarget.isMachoABI();
bool isDarwinABI = Subtarget.isDarwinABI();
// Check if the link register (LR) must be saved.
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
bool MustSaveLR = FI->mustSaveLR();
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
if (Subtarget.isELF32_ABI()) {
if (Subtarget.isSVR4ABI()) {
MachineFrameInfo *FFI = MF.getFrameInfo();
int FPIndex = FI->getFramePointerSaveIndex();
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
}
}
@ -1418,24 +1416,24 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
// Get processor type.
bool IsPPC64 = Subtarget.isPPC64();
// Get operating system
bool IsMachoABI = Subtarget.isMachoABI();
bool isDarwinABI = Subtarget.isDarwinABI();
// Check if the link register (LR) has been saved.
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
bool MustSaveLR = FI->mustSaveLR();
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
if (Subtarget.isELF32_ABI()) {
if (Subtarget.isSVR4ABI()) {
MachineFrameInfo *FFI = MF.getFrameInfo();
int FPIndex = FI->getFramePointerSaveIndex();
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
}
}

2
lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -295,7 +295,7 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
const PPCSubtarget &Subtarget
= MF.getTarget().getSubtarget<PPCSubtarget>();
if (Subtarget.isPPC64() || Subtarget.isELF32_ABI())
if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
return end()-5; // don't allocate R13, R31, R0, R1, LR
if (needsFP(MF))

4
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -148,8 +148,8 @@ public:
/// getDarwinVers - Return the darwin version number, 8 = tiger, 9 = leopard.
unsigned getDarwinVers() const { return DarwinVers; }
bool isMachoABI() const { return isDarwin() || IsPPC64; }
bool isELF32_ABI() const { return !isDarwin() && !IsPPC64; }
bool isDarwinABI() const { return isDarwin() || IsPPC64; }
bool isSVR4ABI() const { return !isDarwin() && !IsPPC64; }
unsigned getAsmFlavor() const {
return AsmFlavor != Unset ? unsigned(AsmFlavor) : 0;