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TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints()
Pass a const reference to LiveRegMatrix to getRegAllocationHints() because some targets can prodive better hints if they can test whether a physreg has been used for register allocation yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242340 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,6 +32,7 @@ class RegScavenger;
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template<class T> class SmallVectorImpl;
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template<class T> class SmallVectorImpl;
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class VirtRegMap;
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class VirtRegMap;
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class raw_ostream;
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class raw_ostream;
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class LiveRegMatrix;
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class TargetRegisterClass {
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class TargetRegisterClass {
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public:
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public:
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@ -709,7 +710,9 @@ public:
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ArrayRef<MCPhysReg> Order,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const MachineFunction &MF,
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const VirtRegMap *VRM = nullptr) const;
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const VirtRegMap *VRM = nullptr,
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const LiveRegMatrix *Matrix = nullptr)
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const;
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/// updateRegAllocHint - A callback to allow target a chance to update
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/// updateRegAllocHint - A callback to allow target a chance to update
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/// register allocation hints when a register is "changed" (e.g. coalesced)
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/// register allocation hints when a register is "changed" (e.g. coalesced)
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@ -29,12 +29,13 @@ using namespace llvm;
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// Compare VirtRegMap::getRegAllocPref().
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder::AllocationOrder(unsigned VirtReg,
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AllocationOrder::AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo)
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix)
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: Pos(0) {
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: Pos(0) {
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const MachineFunction &MF = VRM.getMachineFunction();
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const MachineFunction &MF = VRM.getMachineFunction();
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const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
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const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
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Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
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TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
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rewind();
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rewind();
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DEBUG({
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DEBUG({
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@ -24,6 +24,7 @@ namespace llvm {
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class RegisterClassInfo;
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class RegisterClassInfo;
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class VirtRegMap;
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class VirtRegMap;
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class LiveRegMatrix;
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class LLVM_LIBRARY_VISIBILITY AllocationOrder {
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class LLVM_LIBRARY_VISIBILITY AllocationOrder {
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SmallVector<MCPhysReg, 16> Hints;
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SmallVector<MCPhysReg, 16> Hints;
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@ -37,7 +38,8 @@ public:
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/// @param RegClassInfo Information about reserved and allocatable registers.
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/// @param RegClassInfo Information about reserved and allocatable registers.
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AllocationOrder(unsigned VirtReg,
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AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo);
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix);
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/// Get the allocation order without reordered hints.
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/// Get the allocation order without reordered hints.
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ArrayRef<MCPhysReg> getOrder() const { return Order; }
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ArrayRef<MCPhysReg> getOrder() const { return Order; }
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@ -223,7 +223,7 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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SmallVector<unsigned, 8> PhysRegSpillCands;
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SmallVector<unsigned, 8> PhysRegSpillCands;
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// Check for an available register in this class.
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// Check for an available register in this class.
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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while (unsigned PhysReg = Order.next()) {
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while (unsigned PhysReg = Order.next()) {
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// Check for interference in PhysReg
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// Check for interference in PhysReg
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switch (Matrix->checkInterference(VirtReg, PhysReg)) {
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switch (Matrix->checkInterference(VirtReg, PhysReg)) {
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@ -637,7 +637,7 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
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unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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unsigned PhysReg;
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unsigned PhysReg;
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while ((PhysReg = Order.next())) {
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while ((PhysReg = Order.next())) {
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if (PhysReg == PrevReg)
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if (PhysReg == PrevReg)
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@ -2450,7 +2450,7 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
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unsigned Depth) {
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unsigned Depth) {
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unsigned CostPerUseLimit = ~0u;
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unsigned CostPerUseLimit = ~0u;
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// First try assigning a free register.
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// First try assigning a free register.
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
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if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
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// When NewVRegs is not empty, we may have made decisions such as evicting
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// When NewVRegs is not empty, we may have made decisions such as evicting
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// a virtual register, go with the earlier decisions and use the physical
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// a virtual register, go with the earlier decisions and use the physical
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@ -266,7 +266,8 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const {
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
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std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
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@ -225,7 +225,8 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const {
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
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std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
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@ -126,7 +126,8 @@ public:
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ArrayRef<MCPhysReg> Order,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const override;
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const override;
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const override;
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MachineFunction &MF) const override;
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