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Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -261,6 +261,10 @@ public:
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bool isLiveIn(unsigned Reg) const;
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bool isLiveIn(unsigned Reg) const;
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bool isLiveOut(unsigned Reg) const;
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bool isLiveOut(unsigned Reg) const;
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/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
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/// corresponding live-in physical register.
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unsigned getLiveInPhysReg(unsigned VReg) const;
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// into the given entry block.
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/// into the given entry block.
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void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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@ -147,6 +147,15 @@ bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
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return false;
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return false;
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}
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}
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/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->second == VReg)
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return I->first;
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return 0;
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}
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static cl::opt<bool>
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static cl::opt<bool>
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SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
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SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
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cl::desc("Schedule copies of livein registers"),
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cl::desc("Schedule copies of livein registers"),
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@ -220,30 +229,6 @@ static void EmitLiveInCopy(MachineBasicBlock *MBB,
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}
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}
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}
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}
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/// InsertLiveInDbgValue - Insert a DBG_VALUE instruction for each live-in
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/// register that has a corresponding source information metadata. e.g.
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/// function parameters.
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static void InsertLiveInDbgValue(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator InsertPos,
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unsigned LiveInReg, unsigned VirtReg,
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const MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
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UE = MRI.use_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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if (!UseMI->isDebugValue() || UseMI->getParent() != MBB)
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continue;
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// Found local dbg_value. FIXME: Verify it's not possible to have multiple
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// dbg_value's which reference the vr in the same mbb.
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uint64_t Offset = UseMI->getOperand(1).getImm();
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const MDNode *MDPtr = UseMI->getOperand(2).getMetadata();
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BuildMI(*MBB, InsertPos, InsertPos->getDebugLoc(),
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TII.get(TargetOpcode::DBG_VALUE))
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.addReg(LiveInReg).addImm(Offset).addMetadata(MDPtr);
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return;
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}
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}
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// into the given entry block.
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/// into the given entry block.
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void
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void
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@ -260,8 +245,6 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const TargetRegisterClass *RC = getRegClass(LI->second);
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const TargetRegisterClass *RC = getRegClass(LI->second);
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EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
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EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
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RC, CopyRegMap, *this, TRI, TII);
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RC, CopyRegMap, *this, TRI, TII);
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InsertLiveInDbgValue(EntryMBB, InsertPos,
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LI->first, LI->second, *this, TII);
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}
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}
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} else {
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} else {
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// Emit the copies into the top of the block.
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// Emit the copies into the top of the block.
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@ -273,8 +256,6 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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LI->second, LI->first, RC, RC);
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LI->second, LI->first, RC, RC);
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assert(Emitted && "Unable to issue a live-in copy instruction!\n");
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assert(Emitted && "Unable to issue a live-in copy instruction!\n");
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(void) Emitted;
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(void) Emitted;
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InsertLiveInDbgValue(EntryMBB, EntryMBB->begin(),
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LI->first, LI->second, *this, TII);
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}
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}
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}
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}
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@ -173,6 +173,7 @@ void FunctionLoweringInfo::clear() {
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CatchInfoFound.clear();
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CatchInfoFound.clear();
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#endif
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#endif
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LiveOutRegInfo.clear();
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LiveOutRegInfo.clear();
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ArgDbgValues.clear();
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}
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}
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unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
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unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
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@ -75,6 +75,8 @@ public:
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/// anywhere in the function.
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/// anywhere in the function.
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DenseMap<const AllocaInst*, int> StaticAllocaMap;
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DenseMap<const AllocaInst*, int> StaticAllocaMap;
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SmallVector<MachineInstr*, 8> ArgDbgValues;
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#ifndef NDEBUG
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#ifndef NDEBUG
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SmallSet<const Instruction *, 8> CatchInfoLost;
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SmallSet<const Instruction *, 8> CatchInfoLost;
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SmallSet<const Instruction *, 8> CatchInfoFound;
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SmallSet<const Instruction *, 8> CatchInfoFound;
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@ -3681,6 +3681,41 @@ static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
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return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
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}
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}
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/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
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/// argument, create the corresponding DBG_VALUE machine instruction for it now.
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/// At the end of instruction selection, they will be inserted to the entry BB.
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void
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SelectionDAGBuilder::EmitFuncArgumentDbgValue(const DbgValueInst &DI,
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const Value *V, MDNode *Variable,
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uint64_t Offset, SDValue &N) {
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if (!isa<Argument>(V))
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return;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()];
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if (MBB != &MF.front())
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return;
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unsigned Reg = 0;
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if (N.getOpcode() == ISD::CopyFromReg) {
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Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned PR = RegInfo.getLiveInPhysReg(Reg);
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if (PR)
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Reg = PR;
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}
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}
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if (!Reg)
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Reg = FuncInfo.ValueMap[V];
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const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
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MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
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TII->get(TargetOpcode::DBG_VALUE))
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.addReg(Reg).addImm(Offset).addMetadata(Variable);
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FuncInfo.ArgDbgValues.push_back(&*MIB);
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}
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/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
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/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
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/// we want to emit this as a call to a named external function, return the name
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/// we want to emit this as a call to a named external function, return the name
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@ -3864,6 +3899,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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} else {
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} else {
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SDValue &N = NodeMap[V];
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SDValue &N = NodeMap[V];
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if (N.getNode()) {
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if (N.getNode()) {
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EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N);
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SDV = DAG.getDbgValue(Variable, N.getNode(),
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SDV = DAG.getDbgValue(Variable, N.getNode(),
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N.getResNo(), Offset, dl, SDNodeOrder);
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N.getResNo(), Offset, dl, SDNodeOrder);
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DAG.AddDbgValue(SDV, N.getNode(), false);
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DAG.AddDbgValue(SDV, N.getNode(), false);
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@ -36,6 +36,7 @@ class BasicBlock;
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class BitCastInst;
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class BitCastInst;
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class BranchInst;
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class BranchInst;
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class CallInst;
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class CallInst;
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class DbgValueInst;
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class ExtractElementInst;
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class ExtractElementInst;
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class ExtractValueInst;
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class ExtractValueInst;
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class FCmpInst;
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class FCmpInst;
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@ -58,6 +59,7 @@ class LoadInst;
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class MachineBasicBlock;
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class MachineBasicBlock;
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class MachineInstr;
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class MachineInstr;
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class MachineRegisterInfo;
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class MachineRegisterInfo;
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class MDNode;
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class PHINode;
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class PHINode;
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class PtrToIntInst;
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class PtrToIntInst;
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class ReturnInst;
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class ReturnInst;
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@ -495,6 +497,14 @@ private:
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const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
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const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
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void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a
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/// function argument, create the corresponding DBG_VALUE machine instruction
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/// for it now. At the end of instruction selection, they will be inserted to
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/// the entry BB.
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void EmitFuncArgumentDbgValue(const DbgValueInst &DI,
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const Value *V, MDNode *Variable,
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uint64_t Offset, SDValue &N);
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -212,14 +212,28 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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SelectAllBasicBlocks(Fn);
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SelectAllBasicBlocks(Fn);
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// Release function-specific state. SDB and CurDAG are already cleared
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// at this point.
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FuncInfo->clear();
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// If the first basic block in the function has live ins that need to be
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// If the first basic block in the function has live ins that need to be
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// copied into vregs, emit the copies into the top of the block before
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// copied into vregs, emit the copies into the top of the block before
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// emitting the code for the block.
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// emitting the code for the block.
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RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
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MachineBasicBlock *EntryMBB = MF->begin();
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RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
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// Insert DBG_VALUE instructions for function arguments to the entry block.
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for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
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MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
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unsigned Reg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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EntryMBB->insert(EntryMBB->begin(), MI);
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else {
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MachineInstr *Def = RegInfo->getVRegDef(Reg);
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MachineBasicBlock::iterator InsertPos = Def;
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EntryMBB->insert(llvm::next(InsertPos), MI);
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}
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}
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// Release function-specific state. SDB and CurDAG are already cleared
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// at this point.
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FuncInfo->clear();
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return true;
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return true;
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}
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}
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