mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
[AArch64] Add support for NEON scalar arithmetic instructions:
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
fbe4f5afce
commit
2aeb4771a6
@ -318,9 +318,12 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
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setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
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setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
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setOperationAction(ISD::SETCC, MVT::v1f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
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setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
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}
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}
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@ -2991,6 +2991,40 @@ class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
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[],
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NoItinerary>;
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multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode,
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string asmop, bit Commutable = 0>
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{
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let isCommutable = Commutable in {
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def hhh : NeonI_Scalar3Same<u, 0b01, opcode,
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(outs FPR16:$Rd), (ins FPR16:$Rn, FPR16:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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def sss : NeonI_Scalar3Same<u, 0b10, opcode,
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(outs FPR32:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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}
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}
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multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
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string asmop, bit Commutable = 0>
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{
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let isCommutable = Commutable in {
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def sss : NeonI_Scalar3Same<u, {size_high, 0b0}, opcode,
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(outs FPR32:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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def ddd : NeonI_Scalar3Same<u, {size_high, 0b1}, opcode,
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(outs FPR64:$Rd), (ins FPR64:$Rn, FPR64:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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}
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}
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multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
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string asmop, bit Commutable = 0>
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{
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@ -3018,16 +3052,18 @@ multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
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}
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}
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multiclass Neon_Scalar_D_size_patterns<SDPatternOperator opnode,
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Instruction INSTD> {
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multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
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Instruction INSTD> {
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def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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multiclass Neon_Scalar_BHSD_size_patterns<SDPatternOperator opnode,
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Instruction INSTB, Instruction INSTH,
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Instruction INSTS, Instruction INSTD>
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: Neon_Scalar_D_size_patterns<opnode, INSTD> {
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multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
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Instruction INSTB,
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Instruction INSTH,
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Instruction INSTS,
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Instruction INSTD>
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: Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
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def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
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(INSTB FPR8:$Rn, FPR8:$Rm)>;
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@ -3038,6 +3074,24 @@ multiclass Neon_Scalar_BHSD_size_patterns<SDPatternOperator opnode,
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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}
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multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
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Instruction INSTH,
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Instruction INSTS> {
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def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
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(INSTH FPR16:$Rn, FPR16:$Rm)>;
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def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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}
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multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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// Scalar Integer Add
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let isCommutable = 1 in {
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def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
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@ -3047,14 +3101,14 @@ def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
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def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
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// Pattern for Scalar Integer Add and Sub with D register only
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defm : Neon_Scalar_D_size_patterns<add, ADDddd>;
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defm : Neon_Scalar_D_size_patterns<sub, SUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
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// Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
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// Scalar Integer Saturating Add (Signed, Unsigned)
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defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
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@ -3066,21 +3120,57 @@ defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Saturating Add, Sub (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Saturating Add, Sub (Signed, Unsigned)
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb, SQADDhhh,
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SQADDsss, SQADDddd>;
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb, UQADDhhh,
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UQADDsss, UQADDddd>;
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb, SQSUBhhh,
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SQSUBsss, SQSUBddd>;
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb, UQSUBhhh,
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UQSUBsss, UQSUBddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
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SQADDhhh, SQADDsss, SQADDddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
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UQADDhhh, UQADDsss, UQADDddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
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SQSUBhhh, SQSUBsss, SQSUBddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
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UQSUBhhh, UQSUBsss, UQSUBddd>;
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// Scalar Integer Saturating Doubling Multiply Half High
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defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
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// Scalar Integer Saturating Rounding Doubling Multiply Half High
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defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Saturating Doubling Multiply Half High and
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// Scalar Integer Saturating Rounding Doubling Multiply Half High
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defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
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SQDMULHsss>;
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defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
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SQRDMULHsss>;
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// Scalar Floating-point Multiply Extended
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defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
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// Scalar Floating-point Reciprocal Step
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defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
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// Scalar Floating-point Reciprocal Square Root Step
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defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Floating-point Reciprocal Step and
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// Scalar Floating-point Reciprocal Square Root Step
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defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
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FRECPSddd>;
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defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
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FRSQRTSddd>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Floating-point Multiply Extended,
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defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vmulx, FMULXsss,
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FMULXddd>;
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// Scalar Integer Shift Left (Signed, Unsigned)
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def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
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@ -3088,13 +3178,13 @@ def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
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// Scalar Integer Saturating Shift Left (Signed, Unsigned)
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defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
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@ -3102,15 +3192,15 @@ defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Saturating Shift Letf (Signed, Unsigned)
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb, SQSHLhhh,
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SQSHLsss, SQSHLddd>;
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb, UQSHLhhh,
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UQSHLsss, UQSHLddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
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SQSHLhhh, SQSHLsss, SQSHLddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
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UQSHLhhh, UQSHLsss, UQSHLddd>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Saturating Shift Letf (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
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// Scalar Integer Rounding Shift Left (Signed, Unsigned)
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def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
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@ -3118,13 +3208,13 @@ def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Rounding Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Rounding Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
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// Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
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defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
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@ -3132,15 +3222,15 @@ defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
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// Patterns to match llvm.aarch64.* intrinsic for
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// Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb, SQRSHLhhh,
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SQRSHLsss, SQRSHLddd>;
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defm : Neon_Scalar_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb, UQRSHLhhh,
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UQRSHLsss, UQRSHLddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
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SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
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defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
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UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
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// Patterns to match llvm.arm.* intrinsic for
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// Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
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defm : Neon_Scalar_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
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// Scalar Reduce Pairwise
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@ -4507,3 +4597,7 @@ def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
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def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
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(FMOVdx $src)>;
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def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
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(v1f32 FPR32:$Rn)>;
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def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
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(v1f64 FPR64:$Rn)>;
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70
test/CodeGen/AArch64/neon-scalar-mul.ll
Normal file
70
test/CodeGen/AArch64/neon-scalar-mul.ll
Normal file
@ -0,0 +1,70 @@
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; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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|
||||
define i16 @test_vqdmulhh_s16(i16 %a, i16 %b) {
|
||||
; CHECK: test_vqdmulhh_s16
|
||||
; CHECK: sqdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
|
||||
%1 = insertelement <1 x i16> undef, i16 %a, i32 0
|
||||
%2 = insertelement <1 x i16> undef, i16 %b, i32 0
|
||||
%3 = call <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
|
||||
%4 = extractelement <1 x i16> %3, i32 0
|
||||
ret i16 %4
|
||||
}
|
||||
|
||||
define i32 @test_vqdmulhs_s32(i32 %a, i32 %b) {
|
||||
; CHECK: test_vqdmulhs_s32
|
||||
; CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x i32> undef, i32 %a, i32 0
|
||||
%2 = insertelement <1 x i32> undef, i32 %b, i32 0
|
||||
%3 = call <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
|
||||
%4 = extractelement <1 x i32> %3, i32 0
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
declare <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32>, <1 x i32>)
|
||||
|
||||
define i16 @test_vqrdmulhh_s16(i16 %a, i16 %b) {
|
||||
; CHECK: test_vqrdmulhh_s16
|
||||
; CHECK: sqrdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
|
||||
%1 = insertelement <1 x i16> undef, i16 %a, i32 0
|
||||
%2 = insertelement <1 x i16> undef, i16 %b, i32 0
|
||||
%3 = call <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
|
||||
%4 = extractelement <1 x i16> %3, i32 0
|
||||
ret i16 %4
|
||||
}
|
||||
|
||||
define i32 @test_vqrdmulhs_s32(i32 %a, i32 %b) {
|
||||
; CHECK: test_vqrdmulhs_s32
|
||||
; CHECK: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x i32> undef, i32 %a, i32 0
|
||||
%2 = insertelement <1 x i32> undef, i32 %b, i32 0
|
||||
%3 = call <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
|
||||
%4 = extractelement <1 x i32> %3, i32 0
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
declare <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16>, <1 x i16>)
|
||||
declare <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32>, <1 x i32>)
|
||||
|
||||
define float @test_vmulxs_f32(float %a, float %b) {
|
||||
; CHECK: test_vmulxs_f32
|
||||
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x float> undef, float %a, i32 0
|
||||
%2 = insertelement <1 x float> undef, float %b, i32 0
|
||||
%3 = call <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float> %1, <1 x float> %2)
|
||||
%4 = extractelement <1 x float> %3, i32 0
|
||||
ret float %4
|
||||
}
|
||||
|
||||
define double @test_vmulxd_f64(double %a, double %b) {
|
||||
; CHECK: test_vmulxd_f64
|
||||
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||
%1 = insertelement <1 x double> undef, double %a, i32 0
|
||||
%2 = insertelement <1 x double> undef, double %b, i32 0
|
||||
%3 = call <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double> %1, <1 x double> %2)
|
||||
%4 = extractelement <1 x double> %3, i32 0
|
||||
ret double %4
|
||||
}
|
||||
|
||||
declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)
|
||||
47
test/CodeGen/AArch64/neon-scalar-recip.ll
Normal file
47
test/CodeGen/AArch64/neon-scalar-recip.ll
Normal file
@ -0,0 +1,47 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
|
||||
define float @test_vrecpss_f32(float %a, float %b) {
|
||||
; CHECK: test_vrecpss_f32
|
||||
; CHECK: frecps {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x float> undef, float %a, i32 0
|
||||
%2 = insertelement <1 x float> undef, float %b, i32 0
|
||||
%3 = call <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float> %1, <1 x float> %2)
|
||||
%4 = extractelement <1 x float> %3, i32 0
|
||||
ret float %4
|
||||
}
|
||||
|
||||
define double @test_vrecpsd_f64(double %a, double %b) {
|
||||
; CHECK: test_vrecpsd_f64
|
||||
; CHECK: frecps {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||
%1 = insertelement <1 x double> undef, double %a, i32 0
|
||||
%2 = insertelement <1 x double> undef, double %b, i32 0
|
||||
%3 = call <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double> %1, <1 x double> %2)
|
||||
%4 = extractelement <1 x double> %3, i32 0
|
||||
ret double %4
|
||||
}
|
||||
|
||||
declare <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>)
|
||||
|
||||
define float @test_vrsqrtss_f32(float %a, float %b) {
|
||||
; CHECK: test_vrsqrtss_f32
|
||||
; CHECK: frsqrts {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
%1 = insertelement <1 x float> undef, float %a, i32 0
|
||||
%2 = insertelement <1 x float> undef, float %b, i32 0
|
||||
%3 = call <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float> %1, <1 x float> %2)
|
||||
%4 = extractelement <1 x float> %3, i32 0
|
||||
ret float %4
|
||||
}
|
||||
|
||||
define double @test_vrsqrtsd_f64(double %a, double %b) {
|
||||
; CHECK: test_vrsqrtsd_f64
|
||||
; CHECK: frsqrts {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||
%1 = insertelement <1 x double> undef, double %a, i32 0
|
||||
%2 = insertelement <1 x double> undef, double %b, i32 0
|
||||
%3 = call <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double> %1, <1 x double> %2)
|
||||
%4 = extractelement <1 x double> %3, i32 0
|
||||
ret double %4
|
||||
}
|
||||
|
||||
declare <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>)
|
||||
@ -826,6 +826,33 @@
|
||||
// CHECK-ERROR: uqsub h1, h2, d2
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Integer Saturating Doubling Multiply Half High (Signed)
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
sqdmulh h10, s11, h12
|
||||
sqdmulh s20, h21, s2
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: sqdmulh h10, s11, h12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: sqdmulh s20, h21, s2
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
// Scalar Integer Saturating Rounding Doubling Multiply Half High (Signed)
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
sqrdmulh h10, s11, h12
|
||||
sqrdmulh s20, h21, s2
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: sqrdmulh h10, s11, h12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: sqrdmulh s20, h21, s2
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Vector Shift Left (Signed and Unsigned Integer)
|
||||
@ -3771,3 +3798,44 @@
|
||||
// CHECK-ERROR: fminv d0, v1.2d
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Multiply Extended
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fmulx s20, h22, s15
|
||||
fmulx d23, d11, s1
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fmulx s20, h22, s15
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fmulx d23, d11, s1
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Reciprocal Step
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
frecps s21, s16, h13
|
||||
frecps d22, s30, d21
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: frecps s21, s16, h13
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: frecps d22, s30, d21
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Reciprocal Square Root Step
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
frsqrts s21, h5, s12
|
||||
frsqrts d8, s22, d18
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: frsqrts s21, h5, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: frsqrts d8, s22, d18
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
33
test/MC/AArch64/neon-scalar-mul.s
Normal file
33
test/MC/AArch64/neon-scalar-mul.s
Normal file
@ -0,0 +1,33 @@
|
||||
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
|
||||
|
||||
// Check that the assembler can handle the documented syntax for AArch64
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Integer Saturating Doubling Multiply Half High
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
sqdmulh h10, h11, h12
|
||||
sqdmulh s20, s21, s2
|
||||
|
||||
// CHECK: sqdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x5e]
|
||||
// CHECK: sqdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Integer Saturating Rounding Doubling Multiply Half High
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
sqrdmulh h10, h11, h12
|
||||
sqrdmulh s20, s21, s2
|
||||
|
||||
// CHECK: sqrdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x7e]
|
||||
// CHECK: sqrdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Multiply Extended
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fmulx s20, s22, s15
|
||||
fmulx d23, d11, d1
|
||||
|
||||
// CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e]
|
||||
// CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e]
|
||||
23
test/MC/AArch64/neon-scalar-recip.s
Normal file
23
test/MC/AArch64/neon-scalar-recip.s
Normal file
@ -0,0 +1,23 @@
|
||||
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
|
||||
|
||||
// Check that the assembler can handle the documented syntax for AArch64
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Reciprocal Step
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
frecps s21, s16, s13
|
||||
frecps d22, d30, d21
|
||||
|
||||
// CHECK: frecps s21, s16, s13 // encoding: [0x15,0xfe,0x2d,0x5e]
|
||||
// CHECK: frecps d22, d30, d21 // encoding: [0xd6,0xff,0x75,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Floating-point Reciprocal Square Root Step
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
frsqrts s21, s5, s12
|
||||
frsqrts d8, d22, d18
|
||||
|
||||
// CHECK: frsqrts s21, s5, s12 // encoding: [0xb5,0xfc,0xac,0x5e]
|
||||
// CHECK: frsqrts d8, d22, d18 // encoding: [0xc8,0xfe,0xf2,0x5e]
|
||||
@ -1452,3 +1452,43 @@
|
||||
0x20 0x60 0x22 0x6e
|
||||
0x20 0x60 0x62 0x6e
|
||||
0x20 0x60 0xa2 0x6e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Integer Saturating Doubling Multiply Half High
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: sqdmulh h10, h11, h12
|
||||
# CHECK: sqdmulh s20, s21, s2
|
||||
0x6a,0xb5,0x6c,0x5e
|
||||
0xb4,0xb6,0xa2,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Integer Saturating Rounding Doubling Multiply Half High
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: sqrdmulh h10, h11, h12
|
||||
# CHECK: sqrdmulh s20, s21, s2
|
||||
0x6a,0xb5,0x6c,0x7e
|
||||
0xb4,0xb6,0xa2,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Floating-point multiply extended
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fmulx s20, s22, s15
|
||||
# CHECK: fmulx d23, d11, d1
|
||||
0xd4,0xde,0x2f,0x5e
|
||||
0x77,0xdd,0x61,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Floating-point Reciprocal Step
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: frecps s21, s16, s13
|
||||
# CHECK: frecps d22, d30, d21
|
||||
0x15,0xfe,0x2d,0x5e
|
||||
0xd6,0xff,0x75,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Floating-point Reciprocal Square Root Step
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: frsqrts s21, s5, s12
|
||||
# CHECK: frsqrts d8, d22, d18
|
||||
0xb5,0xfc,0xac,0x5e
|
||||
0xc8,0xfe,0xf2,0x5e
|
||||
|
||||
Loading…
Reference in New Issue
Block a user