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[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov
parent
c5c991bf31
commit
2b01682aa7
@ -3914,10 +3914,10 @@ defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
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defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
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defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
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defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
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defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
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defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
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defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
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defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
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defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">, Requires<[PreV8]>;
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defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">, Requires<[PreV8]>;
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defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">, Requires<[PreV8]>;
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defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">, Requires<[PreV8]>;
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//===----------------------------------------------------------------------===//
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@ -4063,7 +4063,9 @@ def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
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(outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2),
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[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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imm:$CRm, imm:$opc2)]> {
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let Predicates = [IsThumb2, PreV8];
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}
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def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0, pred:$p)>;
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@ -4078,7 +4080,9 @@ def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
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def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
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(outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, imm0_7:$opc2), []>;
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c_imm:$CRm, imm0_7:$opc2), []> {
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let Predicates = [IsThumb2, PreV8];
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}
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def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0, pred:$p)>;
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@ -4096,11 +4100,16 @@ def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
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imm:$CRm)]>;
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def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
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[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
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GPR:$Rt2, imm:$CRm)]>;
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GPR:$Rt2, imm:$CRm)]> {
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let Predicates = [IsThumb2, PreV8];
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}
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/* from coprocessor to ARM core register */
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def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
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def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
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def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1> {
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let Predicates = [IsThumb2, PreV8];
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}
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//===----------------------------------------------------------------------===//
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// Other Coprocessor Instructions.
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@ -4127,6 +4136,8 @@ def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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let Inst{15-12} = CRd;
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let Inst{19-16} = CRn;
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let Inst{23-20} = opc1;
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let Predicates = [IsThumb2, PreV8];
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}
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def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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@ -4150,6 +4161,8 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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let Inst{15-12} = CRd;
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let Inst{19-16} = CRn;
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let Inst{23-20} = opc1;
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let Predicates = [IsThumb2, PreV8];
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}
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File diff suppressed because it is too large
Load Diff
167
test/MC/Disassembler/ARM/invalid-thumbv8.txt
Normal file
167
test/MC/Disassembler/ARM/invalid-thumbv8.txt
Normal file
@ -0,0 +1,167 @@
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# RUN: not llvm-mc -disassemble %s -show-encoding -triple thumbv8 2>&1 | FileCheck %s
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# Coprocessors other than CP10, CP11, CP14 and CP15 are undefined in ARMv8;
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# but in ARMv7, all these instructions are valid
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# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble %s | FileCheck %s --check-prefix=CHECK-V7
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[0x00 0xee 0x00 0x01]
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# CHECK-V7: cdp
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xee 0x00 0x01]
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[0x00 0xee 0x00 0x0e]
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# CHECK-V7: cdp
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xee 0x00 0x0e]
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[0x00 0xee 0x00 0x0f]
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# CHECK-V7: cdp
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xee 0x00 0x0f]
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[0x00 0xfe 0x00 0x01]
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# CHECK-V7: cdp2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x00 0x01]
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[0x00 0xfe 0x00 0x0e]
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# CHECK-V7: cdp2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x00 0x0e]
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[0x00 0xfe 0x00 0x0f]
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# CHECK-V7: cdp2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x00 0x0f]
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[0x00 0xee 0x10 0x01]
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# CHECK-V7: mcr
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xee 0x10 0x01]
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[0x00 0xfe 0x10 0x01]
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# CHECK-V7: mcr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x10 0x01]
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[0x00 0xfe 0x10 0x0e]
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# CHECK-V7: mcr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x10 0x0e]
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[0x00 0xfe 0x10 0x0f]
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# CHECK-V7: mcr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xfe 0x10 0x0f]
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[0x10 0xee 0x10 0x01]
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# CHECK-V7: mrc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x10 0xee 0x10 0x01]
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[0x10 0xfe 0x10 0x01]
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# CHECK-V7: mrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x10 0xfe 0x10 0x01]
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[0x10 0xfe 0x10 0x0e]
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# CHECK-V7: mrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x10 0xfe 0x10 0x0e]
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[0x10 0xfe 0x10 0x0f]
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# CHECK-V7: mrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x10 0xfe 0x10 0x0f]
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[0x40 0xec 0x00 0x01]
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# CHECK-V7: mcrr
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x40 0xec 0x00 0x01]
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[0x40 0xfc 0x00 0x01]
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# CHECK-V7: mcrr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x40 0xfc 0x00 0x01]
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[0x40 0xfc 0x00 0x0e]
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# CHECK-V7: mcrr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x40 0xfc 0x00 0x0e]
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[0x40 0xfc 0x00 0x0f]
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# CHECK-V7: mcrr2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x40 0xfc 0x00 0x0f]
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[0x50 0xec 0x00 0x01]
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# CHECK-V7: mrrc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x50 0xec 0x00 0x01]
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[0x50 0xfc 0x00 0x0e]
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# CHECK-V7: mrrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x50 0xfc 0x00 0x0e]
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[0x50 0xfc 0x00 0x0f]
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# CHECK-V7: mrrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x50 0xfc 0x00 0x0f]
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[0x50 0xfc 0x00 0x01]
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# CHECK-V7: mrrc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x50 0xfc 0x00 0x01]
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[0x80 0xec 0x00 0x01]
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# CHECK-V7: stc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xec 0x00 0x01]
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[0x80 0xec 0x00 0x0f]
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# CHECK-V7: stc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xec 0x00 0x0f]
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[0x80 0xfc 0x00 0x01]
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# CHECK-V7: stc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xfc 0x00 0x01]
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[0x80 0xfc 0x00 0x0e]
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# CHECK-V7: stc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xfc 0x00 0x0e]
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[0x80 0xfc 0x00 0x0f]
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# CHECK-V7: stc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xfc 0x00 0x0f]
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[0x90 0xec 0x00 0x01]
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# CHECK-V7: ldc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x90 0xec 0x00 0x01]
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[0x90 0xec 0x00 0x0f]
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# CHECK-V7: ldc
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x90 0xec 0x00 0x0f]
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[0x90 0xfc 0x00 0x01]
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# CHECK-V7: ldc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x90 0xfc 0x00 0x01]
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[0x90 0xfc 0x00 0x0e]
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# CHECK-V7: ldc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x90 0xfc 0x00 0x0e]
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[0x90 0xfc 0x00 0x0f]
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# CHECK-V7: ldc2
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x90 0xfc 0x00 0x0f]
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@ -3,3 +3,38 @@
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# CHECK: sevl.w
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0x50 0xbf
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0xaf 0xf3 0x05 0x80
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# These are the only coprocessor instructions that remain defined in ARMv8
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# (The operations on p10/p11 disassemble into FP/NEON instructions)
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0x00 0xee 0x10 0x0e
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# CHECK: mcr p14
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0x00 0xee 0x10 0x0f
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# CHECK: mcr p15
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0x10 0xee 0x10 0x0e
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# CHECK: mrc p14
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0x10 0xee 0x10 0x0f
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# CHECK: mrc p15
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0x40 0xec 0x00 0x0e
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# CHECK: mcrr p14
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0x40 0xec 0x00 0x0f
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# CHECK: mcrr p15
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0x50 0xec 0x00 0x0e
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# CHECK: mrrc p14
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0x50 0xec 0x00 0x0f
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# CHECK: mrrc p15
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0x80 0xec 0x00 0x0e
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# CHECK: stc p14
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0x90 0xec 0x00 0x0e
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# CHECK: ldc p14
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