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Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.

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This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-03-16 21:25:05 +00:00
parent 94c484d3b8
commit 2b0272e43d
2 changed files with 10 additions and 2 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1355,7 +1355,9 @@ def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>;
"$addr.addr = $wb", []> {
let Inst{21} = 1; // wback
}
} // mayLoad, hasExtraDefRegAllocReq
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
@ -1368,7 +1370,9 @@ def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iStorem,
"stm${addr:submode}${p}\t$addr!, $srcs",
"$addr.addr = $wb", []>;
"$addr.addr = $wb", []> {
let Inst{21} = 1; // wback
}
} // mayStore, hasExtraSrcRegAllocReq
//===----------------------------------------------------------------------===//

4
lib/Target/ARM/ARMInstrVFP.td
View File

@ -96,6 +96,7 @@ def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
"$addr.base = $wb", []> {
let Inst{21} = 1; // wback
let Inst{20} = 1;
}
@ -104,6 +105,7 @@ def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
"$addr.base = $wb", []> {
let Inst{21} = 1; // wback
let Inst{20} = 1;
}
} // mayLoad, hasExtraDefRegAllocReq
@ -126,6 +128,7 @@ def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
"$addr.base = $wb", []> {
let Inst{21} = 1; // wback
let Inst{20} = 0;
}
@ -134,6 +137,7 @@ def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
"$addr.base = $wb", []> {
let Inst{21} = 1; // wback
let Inst{20} = 0;
}
} // mayStore, hasExtraSrcRegAllocReq