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move some code around, pass in calling conv, even though it is unused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34585 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -423,6 +423,50 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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allowUnalignedMemoryAccesses = true; // x86 supports it!
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}
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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/// GetRetValueLocs - If we are returning a set of values with the specified
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/// value types, determine the set of registers each one will land in. This
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/// sets one element of the ResultRegs array for each element in the VTs array.
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static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
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unsigned *ResultRegs,
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const X86Subtarget *Subtarget,
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unsigned CallingConv) {
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if (NumVTs == 0) return;
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if (NumVTs == 2) {
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ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
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ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
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return;
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}
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// Otherwise, NumVTs is 1.
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MVT::ValueType ArgVT = VTs[0];
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if (MVT::isVector(ArgVT)) // Integer or FP vector result -> XMM0.
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ResultRegs[0] = X86::XMM0;
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else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
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// FP values in X86-64 go in XMM0.
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ResultRegs[0] = X86::XMM0;
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else if (MVT::isFloatingPoint(ArgVT))
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// FP values in X86-32 go in ST0.
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ResultRegs[0] = X86::ST0;
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else {
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assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
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// Integer result -> EAX / RAX.
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// The C calling convention guarantees the return value has been
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// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
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// value to be promoted MVT::i64. So we don't have to extend it to
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// 64-bit.
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ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
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}
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}
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//===----------------------------------------------------------------------===//
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// C & StdCall Calling Convention implementation
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//===----------------------------------------------------------------------===//
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@ -3915,44 +3959,6 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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/// GetRetValueLocs - If we are returning a set of values with the specified
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/// value types, determine the set of registers each one will land in. This
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/// sets one element of the ResultRegs array for each element in the VTs array.
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static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
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unsigned *ResultRegs,
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const X86Subtarget *Subtarget) {
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if (NumVTs == 0) return;
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if (NumVTs == 2) {
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ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
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ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
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return;
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}
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// Otherwise, NumVTs is 1.
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MVT::ValueType ArgVT = VTs[0];
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if (MVT::isVector(ArgVT)) // Integer or FP vector result -> XMM0.
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ResultRegs[0] = X86::XMM0;
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else if (MVT::isFloatingPoint(ArgVT) && Subtarget->is64Bit())
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// FP values in X86-64 go in XMM0.
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ResultRegs[0] = X86::XMM0;
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else if (MVT::isFloatingPoint(ArgVT))
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// FP values in X86-32 go in ST0.
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ResultRegs[0] = X86::ST0;
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else {
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assert(MVT::isInteger(ArgVT) && "Unknown return value type!");
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// Integer result -> EAX / RAX.
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// The C calling convention guarantees the return value has been
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// promoted to at least MVT::i32. The X86-64 ABI doesn't require the
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// value to be promoted MVT::i64. So we don't have to extend it to
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// 64-bit.
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ResultRegs[0] = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
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}
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}
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SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
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assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
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@ -3966,7 +3972,8 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
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VTs[i] = Op.getOperand(i*2+1).getValueType();
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// Determine which register each value should be copied into.
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GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget);
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GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
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DAG.getMachineFunction().getFunction()->getCallingConv());
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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