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[x86] allow 64-bit extracted vector element integer stores on a 32-bit system

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With SSE2, we can generate a 'movq' or other 64-bit store op on a 32-bit system
even though 64-bit integers are not legal types.

So instead of producing this:

  pshufd	$229, %xmm0, %xmm1      ## xmm1 = xmm0[1,1,2,3]
  movd	%xmm0, (%eax)
  movd	%xmm1, 4(%eax)

We can do:

  movq %xmm0, (%eax)

This is a fix for the problem noted in D7296.

Differential Revision: http://reviews.llvm.org/D9134



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2015-04-22 00:24:30 +00:00
parent 8992ead662
commit 2b2b3a87da
2 changed files with 61 additions and 1 deletions
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21
lib/Target/X86/X86ISelLowering.cpp
View File

@ -22948,6 +22948,27 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
MinAlign(St->getAlignment(), 4));
return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
}
// This is similar to the above case, but here we handle a scalar 64-bit
// integer store that is extracted from a vector on a 32-bit target.
// If we have SSE2, then we can treat it like a floating-point double
// to get past legalization. The execution dependencies fixup pass will
// choose the optimal machine instruction for the store if this really is
// an integer or v2f32 rather than an f64.
if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
SDValue OldExtract = St->getOperand(1);
SDValue ExtOp0 = OldExtract.getOperand(0);
unsigned VecSize = ExtOp0.getValueSizeInBits();
MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
BitCast, OldExtract.getOperand(1));
return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
St->getPointerInfo(), St->isVolatile(),
St->isNonTemporal(), St->getAlignment());
}
return SDValue();
}

41
test/CodeGen/X86/i64-mem-copy.ll
View File

@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32AVX
; Use movq or movsd to load / store i64 values if sse2 is available.
; rdar://6659858
@ -18,9 +19,47 @@ define void @foo(i64* %x, i64* %y) {
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: movsd %xmm0, (%eax)
; X32-NEXT: retl
%tmp1 = load i64, i64* %y, align 8
store i64 %tmp1, i64* %x, align 8
ret void
}
; Verify that a 64-bit chunk extracted from a vector is stored with a movq
; regardless of whether the system is 64-bit.
define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, i64* %i) {
; X64-LABEL: store_i64_from_vector:
; X64: # BB#0:
; X64-NEXT: paddw %xmm1, %xmm0
; X64-NEXT: movq %xmm0, (%rdi)
; X64-NEXT: retq
;
; X32-LABEL: store_i64_from_vector:
; X32: # BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: paddw %xmm1, %xmm0
; X32-NEXT: movq %xmm0, (%eax)
; X32-NEXT: retl
%z = add <8 x i16> %x, %y ; force execution domain
%bc = bitcast <8 x i16> %z to <2 x i64>
%vecext = extractelement <2 x i64> %bc, i32 0
store i64 %vecext, i64* %i, align 8
ret void
}
define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, i64* %i) {
; X32AVX-LABEL: store_i64_from_vector256:
; X32AVX: # BB#0:
; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; X32AVX-NEXT: vextracti128 $1, %ymm0, %xmm0
; X32AVX-NEXT: vmovq %xmm0, (%eax)
; X32AVX-NEXT: vzeroupper
; X32AVX-NEXT: retl
%z = add <16 x i16> %x, %y ; force execution domain
%bc = bitcast <16 x i16> %z to <4 x i64>
%vecext = extractelement <4 x i64> %bc, i32 2
store i64 %vecext, i64* %i, align 8
ret void
}