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Add another peephole pattern for conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -83,6 +83,12 @@ multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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}
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multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XORiOp> {
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def : Pat<(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
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}
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multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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Instruction XOROp> {
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Instruction XOROp> {
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def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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@ -170,6 +176,7 @@ let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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// Instantiation of conditional move patterns.
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// Instantiation of conditional move patterns.
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defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
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defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
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defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
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let Predicates = [HasMips64] in {
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let Predicates = [HasMips64] in {
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defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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@ -179,6 +186,9 @@ let Predicates = [HasMips64] in {
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defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
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defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
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defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
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defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
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defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
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defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
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defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
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defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
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defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
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}
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}
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defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
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defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
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@ -37,3 +37,23 @@ entry:
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ret i32 %cond
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ret i32 %cond
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}
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}
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; O32: cmov3:
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; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i32 %b, i32 %c
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ret i32 %cond
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}
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; N64: cmov4:
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; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i64 %b, i64 %c
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ret i64 %cond
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}
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