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Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag selector to generate this, fixing UnitTests/2003-07-06-IntOverflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,7 +40,8 @@ namespace {
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// minor pessimization that saves us from having to worry about
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// keeping the offsets up to date later when we emit long branch glue.
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return 12;
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case PPC::IMPLICIT_DEF: // no asm emitted
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case PPC::IMPLICIT_DEF_GPR: // no asm emitted
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case PPC::IMPLICIT_DEF_FP: // no asm emitted
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return 0;
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default:
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break;
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@ -124,7 +124,8 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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default:
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emitWord(getBinaryCodeForInstr(*I));
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break;
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case PPC::IMPLICIT_DEF:
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case PPC::IMPLICIT_DEF_GPR:
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case PPC::IMPLICIT_DEF_FP:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
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@ -469,7 +469,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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std::cerr << "\n";
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abort();
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case ISD::EntryToken: // These leaves remain the same.
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case ISD::UNDEF:
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return Op;
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case ISD::TokenFactor: {
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SDOperand New;
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@ -525,6 +524,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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break;
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}
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i32)
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
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else
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CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
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break;
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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SDOperand Tmp;
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@ -830,7 +830,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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Node->dump(); std::cerr << '\n';
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assert(0 && "Node not handled!\n");
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case ISD::UNDEF:
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BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
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if (Node->getValueType(0) == MVT::i32)
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BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
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else
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BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
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return Result;
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case ISD::DYNAMIC_STACKALLOC:
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// Generate both result values. FIXME: Need a better commment here?
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@ -1872,8 +1875,11 @@ void ISel::Select(SDOperand N) {
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return;
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case ISD::ImplicitDef:
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Select(N.getOperand(0));
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BuildMI(BB, PPC::IMPLICIT_DEF, 0,
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cast<RegisterSDNode>(N.getOperand(1))->getReg());
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Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
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if (N.getOperand(1).getValueType() == MVT::i32)
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BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
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else
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BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
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return;
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case ISD::RET:
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switch (N.getNumOperands()) {
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@ -64,7 +64,8 @@ let isLoad = 1 in {
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def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
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}
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def IMPLICIT_DEF : Pseudo<(ops variable_ops), "; IMPLICIT_DEF">;
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def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
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def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
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