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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
make BB labels be exported for debuging, add fp negation optimization, further pecimise the FP instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20332 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
5a53c5d197
commit
2b6c4f554b
@ -119,7 +119,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
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case MachineOperand::MO_MachineBasicBlock: {
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MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
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O << "$LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
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O << "LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
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<< "_" << MBBOp->getNumber() << "\t" << CommentString << " "
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<< MBBOp->getBasicBlock()->getName();
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return;
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@ -169,7 +169,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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// Print out labels for the function.
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O << "\t.text\n";
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emitAlignment(4);
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emitAlignment(3);
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.ent\t" << CurrentFnName << "\n";
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@ -179,7 +179,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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O << "$LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
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O << "LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
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<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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@ -190,7 +190,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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}
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++LabelNumber;
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O << "\t.end\t" << CurrentFnName << "\n";
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O << "\t.end " << CurrentFnName << "\n";
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// We didn't modify anything.
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return false;
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@ -447,19 +447,38 @@ void ISel::SelectBranchCC(SDOperand N)
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//a = b: c = 0
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//a < b: c < 0
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//a > b: c > 0
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unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
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unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
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unsigned Tmp3 = MakeReg(MVT::f64);
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BuildMI(BB, Alpha::SUBT, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
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bool invTest = false;
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unsigned Tmp3;
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ConstantFPSDNode *CN;
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if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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Tmp3 = SelectExpr(SetCC->getOperand(0));
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else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp3 = SelectExpr(SetCC->getOperand(1));
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invTest = true;
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}
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else
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{
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unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
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unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
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bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
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Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
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BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
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.addReg(Tmp1).addReg(Tmp2);
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}
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switch (SetCC->getCondition()) {
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default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = Alpha::FBEQ; break;
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case ISD::SETLT: Opc = Alpha::FBLT; break;
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case ISD::SETLE: Opc = Alpha::FBLE; break;
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case ISD::SETGT: Opc = Alpha::FBGT; break;
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case ISD::SETGE: Opc = Alpha::FBGE; break;
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case ISD::SETNE: Opc = Alpha::FBNE; break;
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case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
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case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
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case ISD::SETLE: Opc = invTest ? Alpha::FBGE : Alpha::FBLE; break;
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case ISD::SETGT: Opc = invTest ? Alpha::FBLT : Alpha::FBGT; break;
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case ISD::SETGE: Opc = invTest ? Alpha::FBLE : Alpha::FBGE; break;
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case ISD::SETNE: Opc = invTest ? Alpha::FBEQ : Alpha::FBNE; break;
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}
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BuildMI(BB, Opc, 2).addReg(Tmp3).addMBB(Dest);
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return;
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@ -598,9 +617,19 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS; break;
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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ConstantFPSDNode *CN;
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if (opcode == ISD::SUB
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&& (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
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&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
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{
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
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} else {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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case ISD::EXTLOAD:
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@ -1301,13 +1330,14 @@ unsigned ISel::SelectExpr(SDOperand N) {
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// special calling conventions
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//Restore GP because it is a call after all...
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switch(opcode) {
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case ISD::UREM: AlphaLowering.restoreGP(BB); Opc = Alpha::REMQU; break;
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case ISD::SREM: AlphaLowering.restoreGP(BB); Opc = Alpha::REMQ; break;
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case ISD::UDIV: AlphaLowering.restoreGP(BB); Opc = Alpha::DIVQU; break;
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case ISD::SDIV: AlphaLowering.restoreGP(BB); Opc = Alpha::DIVQ; break;
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case ISD::UREM: Opc = Alpha::REMQU; break;
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case ISD::SREM: Opc = Alpha::REMQ; break;
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case ISD::UDIV: Opc = Alpha::DIVQU; break;
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case ISD::SDIV: Opc = Alpha::DIVQ; break;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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@ -25,7 +25,7 @@ def s21imm : Operand<i32>;
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def s64imm : Operand<i64>;
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def PHI : PseudoInstAlpha<(ops ), "#phi">;
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def IDEF : PseudoInstAlpha<(ops ), "#idef">;
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def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
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def WTF : PseudoInstAlpha<(ops ), "#wtf">;
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def ADJUSTSTACKUP : PseudoInstAlpha<(ops ), "ADJUP">;
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def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
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@ -337,18 +337,19 @@ def CPYSE : FPForm<0x17, 0x022, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpyse $RA,$
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def CPYSN : FPForm<0x17, 0x021, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpysn $RA,$RB,$RC">; //Copy sign negate
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//Basic Floating point ops
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def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds $RA,$RB,$RC">; //Add S_floating
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def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt $RA,$RB,$RC">; //Add T_floating
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def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs $RA,$RB,$RC">; //Subtract S_floating
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def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt $RA,$RB,$RC">; //Subtract T_floating
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def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs $RA,$RB,$RC">; //Divide S_floating
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def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt $RA,$RB,$RC">; //Divide T_floating
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def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls $RA,$RB,$RC">; //Multiply S_floating
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def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult $RA,$RB,$RC">; //Multiply T_floating
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def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds/sui $RA,$RB,$RC">; //Add S_floating
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def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt/sui $RA,$RB,$RC">; //Add T_floating
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def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs/sui $RA,$RB,$RC">; //Subtract S_floating
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def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt/sui $RA,$RB,$RC">; //Subtract T_floating
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def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs/sui $RA,$RB,$RC">; //Divide S_floating
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def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt/sui $RA,$RB,$RC">; //Divide T_floating
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def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls/sui $RA,$RB,$RC">; //Multiply S_floating
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def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult/sui $RA,$RB,$RC">; //Multiply T_floating
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def SQRTS : FPForm<0x14, 0x08B, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrts $RA,$RB,$RC">; //Square root S_floating
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def SQRTT : FPForm<0x14, 0x0AB, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrtt $RA,$RB,$RC">; //Square root T_floating
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//INT reg to FP reg and back again
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//not supported on 21164
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def FTOIS : FPForm<0x1C, 0x078, (ops FPRC:$RC, GPRC:$RA), "ftois $RA,$RC">; //Floating to integer move, S_floating
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def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Floating to integer move, T_floating
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def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating
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