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Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-11 18:55:42 +00:00
parent 3dac0bec7e
commit 2b7b238e84
3 changed files with 4 additions and 5 deletions
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2
lib/Target/ARM/ARMInstrInfo.td
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@ -625,7 +625,7 @@ def ldst_so_reg : Operand<i32>,
let PrintMethod = "printAddrMode2Operand"; let PrintMethod = "printAddrMode2Operand";
let DecoderMethod = "DecodeSORegMemOperand"; let DecoderMethod = "DecodeSORegMemOperand";
let ParserMatchClass = MemRegOffsetAsmOperand; let ParserMatchClass = MemRegOffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift); let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
} }
// postidx_imm8 := +/- [0,255] // postidx_imm8 := +/- [0,255]

2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -979,7 +979,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
idx_mode = ARMII::IndexModePost; idx_mode = ARMII::IndexModePost;
if (reg) { if (reg) {
if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
ARM_AM::ShiftOpc Opc = ARM_AM::lsl; ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
switch( fieldFromInstruction32(Insn, 5, 2)) { switch( fieldFromInstruction32(Insn, 5, 2)) {
case 0: case 0:

5
test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
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@ -1,11 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
# ------------------------------------------------------------------------------------------------- # -------------------------------------------------------------------------------------------------
# #
# if m == 15 then UNPREDICTABLE # if m == 15 then UNPREDICTABLE
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