mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Fix a major miscompilation where we were overwriting the scale reg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
48034fd9f1
commit
2b9378646d
@ -469,7 +469,7 @@ bool ISel::SelectAddress(SDOperand N, X86AddressMode &AM) {
|
||||
AM.Disp += cast<ConstantSDNode>(N)->getValue();
|
||||
return false;
|
||||
case ISD::SHL:
|
||||
if (AM.IndexReg == 0 || AM.Scale == 1)
|
||||
if (AM.IndexReg == 0 && AM.Scale == 1)
|
||||
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
|
||||
unsigned Val = CN->getValue();
|
||||
if (Val == 1 || Val == 2 || Val == 3) {
|
||||
|
Loading…
Reference in New Issue
Block a user