From 2bb644f4692965e4aab98e446d17580cc8613520 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 21 Mar 2015 19:15:46 +0000
Subject: [PATCH] R600: Cleanup test with multiple check prefixes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232901 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/R600/store.ll | 82 +++++++++++++++++++-------------------
 1 file changed, 40 insertions(+), 42 deletions(-)

diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index b5d68d293d9..b51b9b71f70 100644
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -16,7 +16,7 @@ entry:
 }
 
 ; i8 store
-; EG-LABEL: {{^}}store_i8:
+; FUNC-LABEL: {{^}}store_i8:
 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
 
 ; IG 0: Get the byte index and truncate the value
@@ -37,7 +37,6 @@ entry:
 ; EG: MOV T[[RW_GPR]].Y, 0.0
 ; EG: MOV * T[[RW_GPR]].Z, 0.0
 
-; SI-LABEL: {{^}}store_i8:
 ; SI: buffer_store_byte
 
 define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
@@ -47,7 +46,7 @@ entry:
 }
 
 ; i16 store
-; EG-LABEL: {{^}}store_i16:
+; FUNC-LABEL: {{^}}store_i16:
 ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
 
 ; IG 0: Get the byte index and truncate the value
@@ -71,7 +70,6 @@ entry:
 ; EG: MOV T[[RW_GPR]].Y, 0.0
 ; EG: MOV * T[[RW_GPR]].Z, 0.0
 
-; SI-LABEL: {{^}}store_i16:
 ; SI: buffer_store_short
 define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
 entry:
@@ -79,10 +77,10 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v2i8:
+; FUNC-LABEL: {{^}}store_v2i8:
 ; EG: MEM_RAT MSKOR
 ; EG-NOT: MEM_RAT MSKOR
-; SI-LABEL: {{^}}store_v2i8:
+
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
@@ -93,11 +91,11 @@ entry:
 }
 
 
-; EG-LABEL: {{^}}store_v2i16:
+; FUNC-LABEL: {{^}}store_v2i16:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v2i16:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v2i16:
+
 ; SI: buffer_store_short
 ; SI: buffer_store_short
 define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
@@ -107,11 +105,11 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i8:
+; FUNC-LABEL: {{^}}store_v4i8:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v4i8:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v4i8:
+
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
 ; SI: buffer_store_byte
@@ -124,11 +122,11 @@ entry:
 }
 
 ; floating-point store
-; EG-LABEL: {{^}}store_f32:
+; FUNC-LABEL: {{^}}store_f32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
-; CM-LABEL: {{^}}store_f32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
-; SI-LABEL: {{^}}store_f32:
+
 ; SI: buffer_store_dword
 
 define void @store_f32(float addrspace(1)* %out, float %in) {
@@ -136,13 +134,13 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i16:
+; FUNC-LABEL: {{^}}store_v4i16:
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG: MEM_RAT MSKOR
 ; EG-NOT: MEM_RAT MSKOR
-; SI-LABEL: {{^}}store_v4i16:
+
 ; SI: buffer_store_short
 ; SI: buffer_store_short
 ; SI: buffer_store_short
@@ -156,11 +154,11 @@ entry:
 }
 
 ; vec2 floating-point stores
-; EG-LABEL: {{^}}store_v2f32:
+; FUNC-LABEL: {{^}}store_v2f32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v2f32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v2f32:
+
 ; SI: buffer_store_dwordx2
 
 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
@@ -171,13 +169,13 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_v4i32:
+; FUNC-LABEL: {{^}}store_v4i32:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
 ; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}store_v4i32:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
 ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}store_v4i32:
+
 ; SI: buffer_store_dwordx4
 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
 entry:
@@ -218,29 +216,29 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_i8:
+; FUNC-LABEL: {{^}}store_local_i8:
 ; EG: LDS_BYTE_WRITE
-; SI-LABEL: {{^}}store_local_i8:
+
 ; SI: ds_write_b8
 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
   store i8 %in, i8 addrspace(3)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_i16:
+; FUNC-LABEL: {{^}}store_local_i16:
 ; EG: LDS_SHORT_WRITE
-; SI-LABEL: {{^}}store_local_i16:
+
 ; SI: ds_write_b16
 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
   store i16 %in, i16 addrspace(3)* %out
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v2i16:
+; FUNC-LABEL: {{^}}store_local_v2i16:
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v2i16:
+
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v2i16:
+
 ; SI: ds_write_b16
 ; SI: ds_write_b16
 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
@@ -249,11 +247,11 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v4i8:
+; FUNC-LABEL: {{^}}store_local_v4i8:
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v4i8:
+
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v4i8:
+
 ; SI: ds_write_b8
 ; SI: ds_write_b8
 ; SI: ds_write_b8
@@ -264,13 +262,13 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v2i32:
+; FUNC-LABEL: {{^}}store_local_v2i32:
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v2i32:
+
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v2i32:
+
 ; SI: ds_write_b64
 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
 entry:
@@ -278,17 +276,17 @@ entry:
   ret void
 }
 
-; EG-LABEL: {{^}}store_local_v4i32:
+; FUNC-LABEL: {{^}}store_local_v4i32:
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
 ; EG: LDS_WRITE
-; CM-LABEL: {{^}}store_local_v4i32:
+
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
 ; CM: LDS_WRITE
-; SI-LABEL: {{^}}store_local_v4i32:
+
 ; SI: ds_write_b32
 ; SI: ds_write_b32
 ; SI: ds_write_b32
@@ -326,11 +324,11 @@ entry:
 ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
 ; be two 32-bit stores.
 
-; EG-LABEL: {{^}}vecload2:
+; FUNC-LABEL: {{^}}vecload2:
 ; EG: MEM_RAT_CACHELESS STORE_RAW
-; CM-LABEL: {{^}}vecload2:
+
 ; CM: MEM_RAT_CACHELESS STORE_DWORD
-; SI-LABEL: {{^}}vecload2:
+
 ; SI: buffer_store_dwordx2
 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
 entry: