From 2bc210d99f5a7322a1ae84775eba351d9ab6ea85 Mon Sep 17 00:00:00 2001 From: Jim Laskey Date: Thu, 22 Feb 2007 15:37:19 +0000 Subject: [PATCH] Simplify lowering and selection of exception ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34491 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 38 ++++++++++++++++++++++++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 28 +++++++++++++++-- 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index b52b68c9dc6..5aae2583cef 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -403,6 +403,20 @@ public: return StackPointerRegisterToSaveRestore; } + /// getExceptionAddressRegister - If a physical register, this returns + /// the register that receives the exception address on entry to a landing + /// pad. + unsigned getExceptionAddressRegister() const { + return ExceptionPointerRegister; + } + + /// getExceptionSelectorRegister - If a physical register, this returns + /// the register that receives the exception typeid on entry to a landing + /// pad. + unsigned getExceptionSelectorRegister() const { + return ExceptionSelectorRegister; + } + /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never /// set, the default is 200) unsigned getJumpBufSize() const { @@ -604,6 +618,20 @@ protected: StackPointerRegisterToSaveRestore = R; } + /// setExceptionPointerRegister - If set to a physical register, this sets + /// the register that receives the exception address on entry to a landing + /// pad. + void setExceptionPointerRegister(unsigned R) { + ExceptionPointerRegister = R; + } + + /// setExceptionSelectorRegister - If set to a physical register, this sets + /// the register that receives the exception typeid on entry to a landing + /// pad. + void setExceptionSelectorRegister(unsigned R) { + ExceptionSelectorRegister = R; + } + /// SelectIsExpensive - Tells the code generator not to expand operations /// into sequences that use the select operations if possible. void setSelectIsExpensive() { SelectIsExpensive = true; } @@ -956,6 +984,16 @@ private: /// and restore. unsigned StackPointerRegisterToSaveRestore; + /// ExceptionPointerRegister - If set to a physical register, this specifies + /// the register that receives the exception address on entry to a landing + /// pad. + unsigned ExceptionPointerRegister; + + /// ExceptionSelectorRegister - If set to a physical register, this specifies + /// the register that receives the exception typeid on entry to a landing + /// pad. + unsigned ExceptionSelectorRegister; + /// RegClassForVT - This indicates the default register class to use for /// each ValueType the target supports natively. TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 0992e421b1b..d9bb99ec27d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -668,8 +668,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::FRAMEADDR: case ISD::RETURNADDR: - case ISD::EXCEPTIONADDR: - case ISD::EHSELECTION: // The only option for these nodes is to custom lower them. If the target // does not custom lower them, then return zero. Tmp1 = TLI.LowerOperation(Op, DAG); @@ -678,6 +676,32 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { else Result = DAG.getConstant(0, TLI.getPointerTy()); break; + case ISD::EHSELECTION: + LegalizeOp(Node->getOperand(1)); + // Fall Thru + case ISD::EXCEPTIONADDR: { + Tmp1 = LegalizeOp(Node->getOperand(0)); + MVT::ValueType VT = Node->getValueType(0); + switch (TLI.getOperationAction(Node->getOpcode(), VT)) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Expand: { + unsigned Reg = Node->getOpcode() == ISD::EXCEPTIONADDR ? + TLI.getExceptionAddressRegister() : + TLI.getExceptionSelectorRegister(); + Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); + } + break; + case TargetLowering::Custom: + Result = TLI.LowerOperation(Op, DAG); + if (Result.Val) break; + // Fall Thru + case TargetLowering::Legal: + Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp1). + getValue(Op.ResNo); + break; + } + } + break; case ISD::AssertSext: case ISD::AssertZext: Tmp1 = LegalizeOp(Node->getOperand(0));