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ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
d8212b2916
commit
2bd0118472
@ -651,8 +651,10 @@ def postidx_imm8 : Operand<i32> {
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// 9 bit value:
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// {8} 1 is imm8 is non-negative. 0 otherwise.
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// {7-0} [0,255] imm8 value, scaled by 4.
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def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
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def postidx_imm8s4 : Operand<i32> {
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let PrintMethod = "printPostIdxImm8s4Operand";
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let ParserMatchClass = PostIdxImm8s4AsmOperand;
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let MIOperandInfo = (ops i32imm);
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}
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@ -4246,117 +4248,168 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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class ACI<dag oops, dag iops, string opc, string asm,
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IndexMode im = IndexModeNone>
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: InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
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opc, asm, "", []> {
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: I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
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opc, asm, "", []> {
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let Inst{27-25} = 0b110;
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}
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multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
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def _OFFSET : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), ops),
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!strconcat(opc, cond), "\t$cop, $CRd, $addr"> {
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let Inst{31-28} = op31_28;
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class ACInoP<dag oops, dag iops, string opc, string asm,
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IndexMode im = IndexModeNone>
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: InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
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opc, asm, "", []> {
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let Inst{31-28} = 0b1111;
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let Inst{27-25} = 0b110;
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}
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multiclass LdStCop<bit load, bit Dbit, string asm> {
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def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr"> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def _PRE : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), ops),
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!strconcat(opc, cond), "\t$cop, $CRd, $addr!", IndexModePre> {
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let Inst{31-28} = op31_28;
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def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr!", IndexModePre> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def _POST : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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postidx_imm8s4:$offset), ops),
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!strconcat(opc, cond), "\t$cop, $CRd, $addr, $offset",
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IndexModePost> {
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let Inst{31-28} = op31_28;
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def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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postidx_imm8s4:$offset),
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asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
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bits<9> offset;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{23} = offset{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = offset{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def _OPTION : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$base,
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nohash_imm:$option),
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ops),
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!strconcat(opc, cond), "\t$cop, $CRd, $base, \\{$option\\}"> {
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let Inst{31-28} = op31_28;
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(ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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nohash_imm:$option),
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asm, "\t$cop, $CRd, $addr, \\{$option\\}"> {
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bits<8> option;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{22} = 0; // D = 0
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = option;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_OFFSET : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), ops),
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!strconcat(!strconcat(opc, "l"), cond), "\t$cop, $CRd, $addr"> {
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let Inst{31-28} = op31_28;
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}
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multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
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def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr"> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_PRE : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), ops),
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!strconcat(!strconcat(opc, "l"), cond), "\t$cop, $CRd, $addr!",
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IndexModePre> {
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let Inst{31-28} = op31_28;
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def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr!", IndexModePre> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 1; // P = 1
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let Inst{23} = addr{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let Inst{19-16} = addr{12-9};
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = addr{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_POST : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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postidx_imm8s4:$offset), ops),
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!strconcat(!strconcat(opc, "l"), cond), "\t$cop, $CRd, $addr, $offset",
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IndexModePost> {
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let Inst{31-28} = op31_28;
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def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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postidx_imm8s4:$offset),
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asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
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bits<9> offset;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{23} = offset{8};
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let Inst{22} = Dbit;
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let Inst{21} = 1; // W = 1
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = offset{7-0};
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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def L_OPTION : ACI<(outs),
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!con((ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$base,
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nohash_imm:$option),
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ops),
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!strconcat(!strconcat(opc, "l"), cond),
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"\t$cop, $CRd, $base, \\{$option\\}"> {
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let Inst{31-28} = op31_28;
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def _OPTION : ACInoP<(outs),
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(ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
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nohash_imm:$option),
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asm, "\t$cop, $CRd, $addr, \\{$option\\}"> {
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bits<8> option;
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bits<4> addr;
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bits<4> cop;
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bits<4> CRd;
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let Inst{24} = 0; // P = 0
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let Inst{23} = 1; // U = 1
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let Inst{22} = Dbit;
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let Inst{21} = 0; // W = 0
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let Inst{22} = 1; // D = 1
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let Inst{20} = load;
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let Inst{19-16} = addr;
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let Inst{15-12} = CRd;
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let Inst{11-8} = cop;
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let Inst{7-0} = option;
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let DecoderMethod = "DecodeCopMemInstruction";
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}
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}
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defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
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defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
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defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
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defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
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defm LDC : LdStCop <1, 0, "ldc">;
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defm LDCL : LdStCop <1, 1, "ldcl">;
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defm STC : LdStCop <0, 0, "stc">;
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defm STCL : LdStCop <0, 1, "stcl">;
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defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
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defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
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defm STC2 : LdSt2Cop<0, 0, "stc2">;
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defm STC2L : LdSt2Cop<0, 1, "stc2l">;
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//===----------------------------------------------------------------------===//
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// Move between coprocessor and ARM core register.
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@ -874,6 +874,15 @@ public:
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int64_t Val = CE->getValue();
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return (Val > -256 && Val < 256) || (Val == INT32_MIN);
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}
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bool isPostIdxImm8s4() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Val = CE->getValue();
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return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
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(Val == INT32_MIN);
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}
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bool isMSRMask() const { return Kind == k_MSRMask; }
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bool isProcIFlags() const { return Kind == k_ProcIFlags; }
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@ -1356,6 +1365,18 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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assert(CE && "non-constant post-idx-imm8s4 operand!");
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int Imm = CE->getValue();
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bool isAdd = Imm >= 0;
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if (Imm == INT32_MIN) Imm = 0;
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// Immediate is scaled by 4.
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Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
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Inst.addOperand(MCOperand::CreateImm(Imm));
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}
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void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
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@ -3539,8 +3560,9 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
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(Mnemonic == "clrex" && !isThumb()) ||
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(Mnemonic == "nop" && isThumbOne()) ||
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((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
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!isThumb()) ||
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((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
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Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
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Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
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((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
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!isThumb()) ||
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Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
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@ -642,6 +642,87 @@ Lforward:
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@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
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@------------------------------------------------------------------------------
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@ LDC{L}/LDC2{L}
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@------------------------------------------------------------------------------
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ldc2 p0, c8, [r1, #4]
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ldc2 p1, c7, [r2]
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ldc2 p2, c6, [r3, #-224]
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ldc2 p3, c5, [r4, #-120]!
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ldc2 p4, c4, [r5], #16
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ldc2 p5, c3, [r6], #-72
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ldc2l p6, c2, [r7, #4]
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ldc2l p7, c1, [r8]
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ldc2l p8, c0, [r9, #-224]
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ldc2l p9, c1, [r10, #-120]!
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ldc2l p10, c2, [r11], #16
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ldc2l p11, c3, [r12], #-72
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ldc p12, c4, [r0, #4]
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ldc p13, c5, [r1]
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ldc p14, c6, [r2, #-224]
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ldc p15, c7, [r3, #-120]!
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ldc p5, c8, [r4], #16
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ldc p4, c9, [r5], #-72
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ldcl p3, c10, [r6, #4]
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ldcl p2, c11, [r7]
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ldcl p1, c12, [r8, #-224]
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ldcl p0, c13, [r9, #-120]!
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ldcl p6, c14, [r10], #16
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ldcl p7, c15, [r11], #-72
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ldclo p12, c4, [r0, #4]
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ldchi p13, c5, [r1]
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ldccs p14, c6, [r2, #-224]
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ldccc p15, c7, [r3, #-120]!
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ldceq p5, c8, [r4], #16
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ldcgt p4, c9, [r5], #-72
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ldcllt p3, c10, [r6, #4]
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ldclge p2, c11, [r7]
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ldclle p1, c12, [r8, #-224]
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ldclne p0, c13, [r9, #-120]!
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ldcleq p6, c14, [r10], #16
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ldclhi p7, c15, [r11], #-72
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@ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x01,0x80,0x91,0xfd]
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@ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x00,0x71,0x92,0xfd]
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@ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x38,0x62,0x13,0xfd]
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@ CHECK: ldc2 p3, c5, [r4, #-120]! @ encoding: [0x1e,0x53,0x34,0xfd]
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@ CHECK: ldc2 p4, c4, [r5], #16 @ encoding: [0x04,0x44,0xb5,0xfc]
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@ CHECK: ldc2 p5, c3, [r6], #-72 @ encoding: [0x12,0x35,0x36,0xfc]
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@ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0x01,0x26,0xd7,0xfd]
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@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xd8,0xfd]
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@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x59,0xfd]
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@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x7a,0xfd]
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@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0x04,0x2a,0xfb,0xfc]
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@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x12,0x3b,0x7c,0xfc]
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@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed]
|
||||
@ CHECK: ldc p13, c5, [r1] @ encoding: [0x00,0x5d,0x91,0xed]
|
||||
@ CHECK: ldc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x12,0xed]
|
||||
@ CHECK: ldc p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x33,0xed]
|
||||
@ CHECK: ldc p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xb4,0xec]
|
||||
@ CHECK: ldc p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x35,0xec]
|
||||
@ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xed]
|
||||
@ CHECK: ldcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xed]
|
||||
@ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xed]
|
||||
@ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0xed]
|
||||
@ CHECK: ldcl p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xfa,0xec]
|
||||
@ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0xec]
|
||||
|
||||
@ CHECK: ldclo p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0x3d]
|
||||
@ CHECK: ldchi p13, c5, [r1] @ encoding: [0x00,0x5d,0x91,0x8d]
|
||||
@ CHECK: ldchs p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x12,0x2d]
|
||||
@ CHECK: ldclo p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x33,0x3d]
|
||||
@ CHECK: ldceq p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xb4,0x0c]
|
||||
@ CHECK: ldcgt p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x35,0xcc]
|
||||
@ CHECK: ldcllt p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xbd]
|
||||
@ CHECK: ldclge p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xad]
|
||||
@ CHECK: ldclle p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xdd]
|
||||
@ CHECK: ldclne p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0x1d]
|
||||
@ CHECK: ldcleq p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xfa,0x0c]
|
||||
@ CHECK: ldclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0x8c]
|
||||
|
||||
|
||||
@------------------------------------------------------------------------------
|
||||
@ LDM*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user