mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman
parent
8f00ffce50
commit
2bdffe4882
@ -254,6 +254,8 @@ private:
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SDNode *SelectConcatVector(SDNode *N);
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SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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@ -2309,6 +2311,21 @@ SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
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return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
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}
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SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
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SDValue Chain = Node->getOperand(0);
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SDValue In1 = Node->getOperand(1);
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SDValue In2L = Node->getOperand(2);
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SDValue In2H = Node->getOperand(3);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
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const SDValue Ops[] = { In1, In2L, In2H, Chain};
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SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
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MVT::i32, MVT::i32, MVT::Other, Ops,
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array_lengthof(Ops));
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cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
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return ResNode;
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}
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SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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@ -3089,6 +3106,21 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case ISD::CONCAT_VECTORS:
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return SelectConcatVector(N);
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case ARMISD::ATOMOR64_DAG:
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return SelectAtomic64(N, ARM::ATOMOR6432);
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case ARMISD::ATOMXOR64_DAG:
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return SelectAtomic64(N, ARM::ATOMXOR6432);
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case ARMISD::ATOMADD64_DAG:
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return SelectAtomic64(N, ARM::ATOMADD6432);
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case ARMISD::ATOMSUB64_DAG:
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return SelectAtomic64(N, ARM::ATOMSUB6432);
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case ARMISD::ATOMNAND64_DAG:
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return SelectAtomic64(N, ARM::ATOMNAND6432);
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case ARMISD::ATOMAND64_DAG:
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return SelectAtomic64(N, ARM::ATOMAND6432);
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case ARMISD::ATOMSWAP64_DAG:
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return SelectAtomic64(N, ARM::ATOMSWAP6432);
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}
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return SelectCode(N);
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@ -611,6 +611,13 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// normally.
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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// Custom lowering for 64-bit ops
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
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// Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
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setInsertFencesForAtomic(true);
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} else {
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@ -4846,6 +4853,29 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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Op.getOperand(1), Op.getOperand(2));
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}
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static void
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ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
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SelectionDAG &DAG, unsigned NewOp) {
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EVT T = Node->getValueType(0);
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DebugLoc dl = Node->getDebugLoc();
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assert (T == MVT::i64 && "Only know how to expand i64 atomics");
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SDValue Chain = Node->getOperand(0);
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SDValue In1 = Node->getOperand(1);
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SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
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Node->getOperand(2), DAG.getIntPtrConstant(0));
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SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
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Node->getOperand(2), DAG.getIntPtrConstant(1));
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SDValue Ops[] = { Chain, In1, In2L, In2H };
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SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
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SDValue Result =
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DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
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cast<MemSDNode>(Node)->getMemOperand());
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SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
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Results.push_back(Result.getValue(2));
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}
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SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Don't know how to custom lower this!");
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@ -4918,6 +4948,29 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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case ISD::SRA:
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Res = Expand64BitShift(N, DAG, Subtarget);
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break;
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case ISD::ATOMIC_LOAD_ADD:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
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return;
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case ISD::ATOMIC_LOAD_AND:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
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return;
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case ISD::ATOMIC_LOAD_NAND:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
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return;
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case ISD::ATOMIC_LOAD_OR:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
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return;
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case ISD::ATOMIC_LOAD_SUB:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
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return;
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case ISD::ATOMIC_LOAD_XOR:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
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return;
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case ISD::ATOMIC_SWAP:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
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return;
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//case ISD::ATOMIC_CMP_SWAP:
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// ReplaceATOMIC_CMPXCHG_64(N, Results, DAG);
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}
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if (Res.getNode())
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Results.push_back(Res);
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@ -5237,6 +5290,113 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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return BB;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Op1, unsigned Op2,
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bool NeedsCarry) const {
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// This also handles ATOMIC_SWAP, indicated by Op1==0.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction *MF = BB->getParent();
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MachineFunction::iterator It = BB;
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++It;
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unsigned destlo = MI->getOperand(0).getReg();
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unsigned desthi = MI->getOperand(1).getReg();
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unsigned ptr = MI->getOperand(2).getReg();
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unsigned vallo = MI->getOperand(3).getReg();
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unsigned valhi = MI->getOperand(4).getReg();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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if (isThumb2) {
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MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
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MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
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MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
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}
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unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
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unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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exitMBB->transferSuccessorsAndUpdatePHIs(BB);
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TargetRegisterClass *TRC =
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isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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unsigned storesuccess = MRI.createVirtualRegister(TRC);
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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BB->addSuccessor(loopMBB);
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// loopMBB:
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// ldrexd r2, r3, ptr
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// <binopa> r0, r2, incr
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// <binopb> r1, r3, incr
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// strexd storesuccess, r0, r1, ptr
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// cmp storesuccess, #0
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// bne- loopMBB
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// fallthrough --> exitMBB
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//
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// Note that the registers are explicitly specified because there is not any
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// way to force the register allocator to allocate a register pair.
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//
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// FIXME: The hardcoded registers are not necessary for Thumb2, but we
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// need to properly enforce the restriction that the two output registers
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// for ldrexd must be different.
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BB = loopMBB;
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// Load
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
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.addReg(ARM::R2, RegState::Define)
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.addReg(ARM::R3, RegState::Define).addReg(ptr));
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// Copy r2/r3 into dest. (This copy will normally be coalesced.)
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
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if (Op1) {
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// Perform binary operation
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
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.addReg(destlo).addReg(vallo))
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.addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
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.addReg(desthi).addReg(valhi)).addReg(0);
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} else {
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// Copy to physregs for strexd
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
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BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
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}
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// Store
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
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.addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
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// Cmp+jump
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(storesuccess).addImm(0));
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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// exitMBB:
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// ...
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BB = exitMBB;
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MI->eraseFromParent(); // The instruction is gone now.
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return BB;
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}
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static
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MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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@ -5374,6 +5534,25 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
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case ARM::ATOMADD6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
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isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, true);
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case ARM::ATOMSUB6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, true);
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case ARM::ATOMOR6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
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isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, false);
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case ARM::ATOMXOR6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
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isThumb2 ? ARM::t2EORrr : ARM::EORrr, false);
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case ARM::ATOMAND6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
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isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, false);
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case ARM::ATOMSWAP6432:
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return EmitAtomicBinary64(MI, BB, 0, 0, false);
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -211,7 +211,17 @@ namespace llvm {
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VST4_UPD,
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VST2LN_UPD,
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VST3LN_UPD,
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VST4LN_UPD
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VST4LN_UPD,
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// 64-bit atomic ops (value split into two registers)
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ATOMADD64_DAG,
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ATOMSUB64_DAG,
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ATOMOR64_DAG,
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ATOMXOR64_DAG,
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMSWAP64_DAG,
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ATOMCMPXCHG64_DAG
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};
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}
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@ -493,6 +503,11 @@ namespace llvm {
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MachineBasicBlock *BB,
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unsigned Size,
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unsigned BinOpcode) const;
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MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Op1,
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unsigned Op2,
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bool NeedsCarry) const;
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MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size,
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@ -69,6 +69,8 @@ def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
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def SDTARMatomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
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SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
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def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
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[SDTCisSameAs<0, 2>,
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@ -162,6 +164,28 @@ def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
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def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
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def ARMAtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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def ARMAtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTARMatomicBinary,
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[SDNPHasChain, SDNPMayStore,
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SDNPMayLoad, SDNPMemOperand]>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Predicate Definitions.
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//
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@ -1609,6 +1633,32 @@ PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
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[(ARMcallseq_start timm:$amt)]>;
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}
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// Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
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// (These psuedos use a hand-written selection code).
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let usesCustomInserter = 1, Uses = [CPSR] in {
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def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
|
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def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
|
||||
(ins GPR:$addr, GPR:$src1, GPR:$src2),
|
||||
NoItinerary, []>;
|
||||
}
|
||||
|
||||
def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
|
||||
Requires<[IsARM, HasV6T2]> {
|
||||
let Inst{27-16} = 0b001100100000;
|
||||
|
||||
83
test/CodeGen/ARM/atomic-64bit.ll
Normal file
83
test/CodeGen/ARM/atomic-64bit.ll
Normal file
@ -0,0 +1,83 @@
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
|
||||
|
||||
define i64 @test1(i64* %ptr, i64 %val) {
|
||||
; CHECK: test1
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: adds r0, r2
|
||||
; CHECK: adc r1, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw add i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @test2(i64* %ptr, i64 %val) {
|
||||
; CHECK: test2
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: subs r0, r2
|
||||
; CHECK: sbc r1, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw sub i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @test3(i64* %ptr, i64 %val) {
|
||||
; CHECK: test3
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: and r0, r2
|
||||
; CHECK: and r1, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw and i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @test4(i64* %ptr, i64 %val) {
|
||||
; CHECK: test4
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: orr r0, r2
|
||||
; CHECK: orr r1, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw or i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @test5(i64* %ptr, i64 %val) {
|
||||
; CHECK: test5
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: eor r0, r2
|
||||
; CHECK: eor r1, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw xor i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define i64 @test6(i64* %ptr, i64 %val) {
|
||||
; CHECK: test6
|
||||
; CHECK: dmb ish
|
||||
; CHECK: ldrexd r2, r3
|
||||
; CHECK: strexd {{r[0-9]+}}, r0, r1
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
%r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user