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Add a perf optzn corresponding to PR1033.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32229 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,6 +18,11 @@ Think about doing i64 math in SSE regs.
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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Bitcast to<->from SSE registers should use movd/movq instead of going through
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the stack. Testcase here: CodeGen/X86/bitcast.ll
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//===---------------------------------------------------------------------===//
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This testcase should have no SSE instructions in it, and only one load from
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This testcase should have no SSE instructions in it, and only one load from
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a constant pool:
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a constant pool:
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