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Simplify a few more uses of reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1087,11 +1087,9 @@ LiveIntervals::isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt
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SmallVector<MachineInstr*,16> &OtherCopies) {
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bool HaveConflict = false;
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unsigned NumIdent = 0;
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for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(SrcInt.reg),
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re = mri_->reg_end(); ri != re; ++ri) {
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for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg),
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re = mri_->def_end(); ri != re; ++ri) {
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MachineOperand &O = ri.getOperand();
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if (!O.isDef())
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continue;
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MachineInstr *MI = &*ri;
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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@ -110,11 +110,9 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
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MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
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assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
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"Invalid vreg!");
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for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
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// Since we are in SSA form, we can stop at the first definition.
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if (I.getOperand().isDef())
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return &*I;
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}
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// Since we are in SSA form, we can use the first definition.
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if (!def_empty(Reg))
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return &*def_begin(Reg);
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return 0;
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}
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@ -397,10 +397,10 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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// Remove unnecessary kills since a copy does not clobber the register.
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if (li_->hasInterval(SrcReg)) {
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LiveInterval &SrcLI = li_->getInterval(SrcReg);
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for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
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E = mri_->reg_end(); I != E; ++I) {
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for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
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E = mri_->use_end(); I != E; ++I) {
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MachineOperand &O = I.getOperand();
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if (!O.isUse() || !O.isKill())
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if (!O.isKill())
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continue;
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MachineInstr *MI = &*I;
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if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
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