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Simplify a few more uses of reg_iterator.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-09-25 22:26:13 +00:00
parent 29438d13e0
commit 2bf0649e05
3 changed files with 8 additions and 12 deletions
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6
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -1087,11 +1087,9 @@ LiveIntervals::isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt
SmallVector<MachineInstr*,16> &OtherCopies) {
bool HaveConflict = false;
unsigned NumIdent = 0;
for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(SrcInt.reg),
re = mri_->reg_end(); ri != re; ++ri) {
for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg),
re = mri_->def_end(); ri != re; ++ri) {
MachineOperand &O = ri.getOperand();
if (!O.isDef())
continue;
MachineInstr *MI = &*ri;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;

8
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -110,11 +110,9 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
"Invalid vreg!");
for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
// Since we are in SSA form, we can stop at the first definition.
if (I.getOperand().isDef())
return &*I;
}
// Since we are in SSA form, we can use the first definition.
if (!def_empty(Reg))
return &*def_begin(Reg);
return 0;
}

6
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -397,10 +397,10 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
// Remove unnecessary kills since a copy does not clobber the register.
if (li_->hasInterval(SrcReg)) {
LiveInterval &SrcLI = li_->getInterval(SrcReg);
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
E = mri_->reg_end(); I != E; ++I) {
for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
E = mri_->use_end(); I != E; ++I) {
MachineOperand &O = I.getOperand();
if (!O.isUse() || !O.isKill())
if (!O.isKill())
continue;
MachineInstr *MI = &*I;
if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))