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Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-11-08 21:42:32 +00:00
parent 85c3f24da3
commit 2c2304c623
3 changed files with 22 additions and 12 deletions
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29
lib/Target/Mips/Mips.td
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@ -36,19 +36,15 @@ def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">; "Support 64-bit FP registers.">;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">; "true", "Only supports single precision float">;
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
"Mips1 ISA Support">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
"Enable o32 ABI">; "Enable o32 ABI">;
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
"Enable eabi ABI">; "Enable eabi ABI">;
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
"true", "Enable vector FPU instructions.">; "true", "Enable vector FPU instructions.">;
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
"Enable 'signext in register' instructions.">; "Enable 'signext in register' instructions.">;
def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
"Enable 'conditional move' instructions.">; "Enable 'conditional move' instructions.">;
def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
"Enable 'multiply add/sub' instructions.">; "Enable 'multiply add/sub' instructions.">;
@ -58,6 +54,15 @@ def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
"Enable 'byte/half swap' instructions.">; "Enable 'byte/half swap' instructions.">;
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
"Enable 'count leading bits' instructions.">; "Enable 'count leading bits' instructions.">;
def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
"Mips1 ISA Support">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support", [FeatureCondMov]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Mips processors supported. // Mips processors supported.
@ -73,10 +78,12 @@ def : Proc<"r3000", [FeatureMips1]>;
def : Proc<"mips2", [FeatureMips2]>; def : Proc<"mips2", [FeatureMips2]>;
def : Proc<"r6000", [FeatureMips2]>; def : Proc<"r6000", [FeatureMips2]>;
// Allegrex is a 32bit subset of r4000, both for interger and fp registers, def : Proc<"4ke", [FeatureMips32r2]>;
// but much more similar to Mips2 than Mips3. It also contains some of
// Mips32/Mips32r2 instructions and a custom vector fpu processor. // Allegrex is a 32bit subset of r4000, both for interger and fp registers,
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, // but much more similar to Mips2 than Mips3. It also contains some of
// Mips32/Mips32r2 instructions and a custom vector fpu processor.
def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd, FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
FeatureMinMax, FeatureSwap, FeatureBitCount]>; FeatureMinMax, FeatureSwap, FeatureBitCount]>;

3
lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -59,7 +59,8 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB)
{ {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
if (I->getDesc().hasDelaySlot()) { if (TM.getSubtarget<MipsSubtarget>().isMips1() &&
I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I; MachineBasicBlock::iterator J = I;
++J; ++J;
BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP)); BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));

2
lib/Target/Mips/MipsSubtarget.h
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@ -100,6 +100,8 @@ public:
const std::string &CPU); const std::string &CPU);
bool isMips1() const { return MipsArchVersion == Mips1; } bool isMips1() const { return MipsArchVersion == Mips1; }
bool isMips32() const { return MipsArchVersion == Mips32; }
bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
bool isLittle() const { return IsLittle; } bool isLittle() const { return IsLittle; }
bool isFP64bit() const { return IsFP64bit; } bool isFP64bit() const { return IsFP64bit; }